From 7fb2a9879ec43e5e1589a131adfffbb5d5d56aca Mon Sep 17 00:00:00 2001
From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Tue, 11 Apr 2023 21:27:25 +0300
Subject: [PATCH] ppc: refactor assembly logic

---
 gas/config/tc-ppc-svp64.c | 17 ++++++++++++++---
 gas/config/tc-ppc.c       | 15 +++++++++++++--
 2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/gas/config/tc-ppc-svp64.c b/gas/config/tc-ppc-svp64.c
index 91977b9d45a..bf8c0c947b7 100644
--- a/gas/config/tc-ppc-svp64.c
+++ b/gas/config/tc-ppc-svp64.c
@@ -591,8 +591,12 @@ static void
 svp64_decode (char *str, struct svp64_ctx *svp64)
 {
   char *opc;
+  size_t opclen;
+  char *args;
+  size_t argslen;
   char *iter;
   const struct svp64_record *record;
+  char *base = str;
 
   str += (sizeof ("sv.") - 1);
   if (! ISALPHA (*str))
@@ -601,6 +605,7 @@ svp64_decode (char *str, struct svp64_ctx *svp64)
   opc = str;
   for (; ! ISSPACE (*str) && *str != SVP64_SEP && *str != '\0'; ++str)
     ;
+  opclen = (str - opc);
   if (*str != '\0')
     *str++ = '\0';
 
@@ -614,6 +619,14 @@ svp64_decode (char *str, struct svp64_ctx *svp64)
 
   for (; (iter = svp64_decode_mode (str, svp64)) != NULL; str = iter)
     ;
+
+  args = str;
+  argslen = strlen (args);
+
+  memmove (base, opc, opclen);
+  base[opclen] = ' ';
+  memmove ((base + opclen + 1), args, argslen);
+  base[opclen + 1 + argslen] = '\0';
 }
 
 static void
@@ -862,7 +875,5 @@ svp64_assemble (char *str)
   svp64_decode (str, &svp64);
   svp64_validate_and_fix (&svp64);
 
-  as_warn (_("opcode ignored (desc=%p)"), svp64.desc);
-  memcpy (str, "nop", sizeof ("nop"));
-  md_assemble (str);
+  ppc_assemble (str, &svp64);
 }
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index d62e671ac52..537d3561bb5 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -36,6 +36,11 @@
 #include "libxcoff.h"
 #endif
 
+struct svp64_ctx;
+
+static void
+ppc_assemble (char *str, struct svp64_ctx *svp64 ATTRIBUTE_UNUSED);
+
 #include "tc-ppc-svp64.c"
 
 /* This is the assembler for the PowerPC or POWER (RS/6000) chips.  */
@@ -3310,8 +3315,8 @@ is_svp64_insn (char *str)
 
 /* This routine is called for each instruction to be assembled.  */
 
-void
-md_assemble (char *str)
+static void
+ppc_assemble (char *str, struct svp64_ctx *svp64 ATTRIBUTE_UNUSED)
 {
   char *s;
   const struct powerpc_opcode *opcode;
@@ -3338,6 +3343,7 @@ md_assemble (char *str)
     {
       if (is_svp64_insn (str))
         {
+          *(s - 1) = ' '; /* restore the original string */
           svp64_assemble (str);
           return;
         }
@@ -4161,6 +4167,11 @@ md_assemble (char *str)
     }
 }
 
+void
+md_assemble (char *str)
+{
+  ppc_assemble (str, NULL);
+}
 
 #ifdef OBJ_ELF
 /* For ELF, add support for SHT_ORDERED.  */
-- 
2.30.2