From 7fb7704b2ea519fb8aae6dc2002d48104b30214d Mon Sep 17 00:00:00 2001
From: Kenneth Graunke <kenneth@whitecape.org>
Date: Tue, 8 May 2018 23:52:07 -0700
Subject: [PATCH] iris: more depth stuffs...

still missing stencil
---
 src/gallium/drivers/iris/iris_context.h |  2 +
 src/gallium/drivers/iris/iris_state.c   | 87 +++++++++++++++++++++----
 2 files changed, 77 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h
index 0be4a313258..50942198f5f 100644
--- a/src/gallium/drivers/iris/iris_context.h
+++ b/src/gallium/drivers/iris/iris_context.h
@@ -85,6 +85,7 @@ struct blorp_params;
 #define IRIS_DIRTY_CONSTANTS_TES            (1ull << 37)
 #define IRIS_DIRTY_CONSTANTS_GS             (1ull << 38)
 #define IRIS_DIRTY_CONSTANTS_FS             (1ull << 39)
+#define IRIS_DIRTY_DEPTH_BUFFER             (1ull << 40)
 
 enum brw_param_domain {
    BRW_PARAM_DOMAIN_BUILTIN = 0,
@@ -270,6 +271,7 @@ struct iris_context {
       struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
       struct pipe_stencil_ref stencil_ref;
       struct pipe_framebuffer_state framebuffer;
+      struct iris_depth_buffer_state *cso_depthbuffer;
 
       struct pipe_resource *sampler_table_resource[MESA_SHADER_STAGES];
       uint32_t sampler_table_offset[MESA_SHADER_STAGES];
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 2e6204395fc..722540f7694 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1250,11 +1250,12 @@ iris_set_viewport_states(struct pipe_context *ctx,
    ice->state.dirty |= IRIS_DIRTY_SF_CL_VIEWPORT;
 }
 
-struct iris_depth_state
+struct iris_depth_buffer_state
 {
-   uint32_t depth_buffer[GENX(3DSTATE_DEPTH_BUFFER_length)];
-   uint32_t hier_depth_buffer[GENX(3DSTATE_HIER_DEPTH_BUFFER_length)];
-   uint32_t stencil_buffer[GENX(3DSTATE_STENCIL_BUFFER_length)];
+   uint32_t packets[GENX(3DSTATE_DEPTH_BUFFER_length) +
+                    GENX(3DSTATE_STENCIL_BUFFER_length) +
+                    GENX(3DSTATE_HIER_DEPTH_BUFFER_length) +
+                    GENX(3DSTATE_CLEAR_PARAMS_length)];
 };
 
 static void
@@ -1262,6 +1263,8 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
                            const struct pipe_framebuffer_state *state)
 {
    struct iris_context *ice = (struct iris_context *) ctx;
+   struct iris_screen *screen = (struct iris_screen *)ctx->screen;
+   struct isl_device *isl_dev = &screen->isl_dev;
    struct pipe_framebuffer_state *cso = &ice->state.framebuffer;
 
    if (cso->samples != state->samples) {
@@ -1287,11 +1290,63 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
 
    pipe_surface_reference(&cso->zsbuf, state->zsbuf);
 
-   //struct isl_depth_stencil_hiz_emit_info info = {
-      //.mocs = MOCS_WB,
-   //};
+   struct iris_depth_buffer_state *cso_z =
+      malloc(sizeof(struct iris_depth_buffer_state));
+
+   struct isl_view view = {
+      /* Some nice defaults */
+      .base_level = 0,
+      .levels = 1,
+      .base_array_layer = 0,
+      .array_len = 1,
+      .swizzle = ISL_SWIZZLE_IDENTITY,
+   };
+
+   struct isl_depth_stencil_hiz_emit_info info = {
+      .view = &view,
+      .mocs = MOCS_WB,
+   };
+
+   struct iris_resource *zres =
+      (void *) (cso->zsbuf ? cso->zsbuf->texture : NULL);
+
+   if (zres) {
+      view.usage |= ISL_SURF_USAGE_DEPTH_BIT;
+
+      info.depth_surf = &zres->surf;
+      info.depth_address = zres->bo->gtt_offset;
+
+      view.format = zres->surf.format;
+
+      view.base_level = cso->zsbuf->u.tex.level;
+      view.base_array_layer = cso->zsbuf->u.tex.first_layer;
+      view.array_len =
+         cso->zsbuf->u.tex.last_layer - cso->zsbuf->u.tex.first_layer + 1;
+
+      info.hiz_usage = ISL_AUX_USAGE_NONE;
+   }
+
+#if 0
+   if (stencil_mt) {
+      view.usage |= ISL_SURF_USAGE_STENCIL_BIT;
+      info.stencil_surf = &stencil_mt->surf;
+
+      if (!depth_mt) {
+         view.base_level = stencil_irb->mt_level - stencil_irb->mt->first_level;
+         view.base_array_layer = stencil_irb->mt_layer;
+         view.array_len = MAX2(stencil_irb->layer_count, 1);
+         view.format = stencil_mt->surf.format;
+      }
+
+      uint32_t stencil_offset = 0;
+      info.stencil_address = stencil_mt->bo->gtt_offset + stencil_mt->offset;
+   }
+#endif
 
-   // XXX: depth buffers
+   isl_emit_depth_stencil_hiz_s(isl_dev, cso_z->packets, &info);
+
+   ice->state.cso_depthbuffer = cso_z;
+   ice->state.dirty |= IRIS_DIRTY_DEPTH_BUFFER;
 }
 
 static void
@@ -2353,10 +2408,18 @@ iris_upload_render_state(struct iris_context *ice,
       }
    }
 
-   // XXX: 3DSTATE_DEPTH_BUFFER
-   // XXX: 3DSTATE_HIER_DEPTH_BUFFER
-   // XXX: 3DSTATE_STENCIL_BUFFER
-   // XXX: 3DSTATE_CLEAR_PARAMS
+   if (dirty & IRIS_DIRTY_DEPTH_BUFFER) {
+      struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
+      struct iris_depth_buffer_state *cso_z = ice->state.cso_depthbuffer;
+
+      iris_batch_emit(batch, cso_z->packets, sizeof(cso_z->packets));
+
+      if (cso_fb->zsbuf) {
+         struct iris_resource *zres = (void *) cso_fb->zsbuf->texture;
+         // XXX: depth might not be writable...
+         iris_use_pinned_bo(batch, zres->bo, true);
+      }
+   }
 
    if (dirty & IRIS_DIRTY_POLYGON_STIPPLE) {
       iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
-- 
2.30.2