From 7fcfba6cd7bd20a2df28a581faaf4fc4cbf8a961 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 1 Jun 2020 05:39:25 +0100 Subject: [PATCH] swap over SPR1/2 to fit with microwatt SPR conventions --- src/soc/fu/branch/formal/proof_main_stage.py | 5 +++-- src/soc/fu/branch/pipe_data.py | 6 +++--- src/soc/fu/branch/test/test_pipe_caller.py | 6 +++--- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/src/soc/fu/branch/formal/proof_main_stage.py b/src/soc/fu/branch/formal/proof_main_stage.py index 2ff11b68..32a29651 100644 --- a/src/soc/fu/branch/formal/proof_main_stage.py +++ b/src/soc/fu/branch/formal/proof_main_stage.py @@ -57,10 +57,11 @@ class Driver(Elaboratable): cr_arr = Array([cr[(7-i)*4:(7-i)*4+4] for i in range(8)]) cr_bit_arr = Array([cr[31-i] for i in range(32)]) - cia, cr_in, spr1, ctr = dut.i.cia, dut.i.cr, dut.i.spr1, dut.i.spr2 + cia, cr_in, spr1, spr2 = dut.i.cia, dut.i.cr, dut.i.spr1, dut.i.spr2 + ctr = spr1 lr_o, nia_o = dut.o.lr, dut.o.nia - comb += [spr1.eq(AnyConst(64)), + comb += [spr2.eq(AnyConst(64)), ctr.eq(AnyConst(64)), cia.eq(AnyConst(64))] diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py index b5aa4c0f..f32872b1 100644 --- a/src/soc/fu/branch/pipe_data.py +++ b/src/soc/fu/branch/pipe_data.py @@ -5,7 +5,7 @@ * CR is Condition Register (not an SPR) * SPR1 and SPR2 are all from the SPR regfile. 2 ports are needed - insn CR SPR1 SPR2 + insn CR SPR2 SPR1 ---- -- ---- ---- op_b xx xx xx op_ba xx xx xx @@ -47,8 +47,8 @@ class BranchInputData(IntegerData): self.cia = Signal(64, reset_less=True) # Current Instruction Address # convenience variables. not all of these are used at once - self.ctr = self.srr0 = self.hsrr0 = self.spr2 - self.lr = self.tar = self.srr1 = self.hsrr1 = self.spr1 + self.ctr = self.srr0 = self.hsrr0 = self.spr1 + self.lr = self.tar = self.srr1 = self.hsrr1 = self.spr2 def __iter__(self): yield from super().__iter__() diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index 541b56dd..c9e059b4 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -153,11 +153,11 @@ class TestRunner(FHDLTestCase): yield branch.p.data_i.cia.eq(simulator.pc.CIA.value) # note, here, the op will need further decoding in order # to set the correct SPRs on SPR1/2/3. op_bc* require - # spr2 to be set to CTR, op_bctar require spr1 to be - # set to TAR, op_bclr* require spr1 to be set to LR. + # spr1 to be set to CTR, op_bctar require spr2 to be + # set to TAR, op_bclr* require spr2 to be set to LR. # if op_sc*, op_rf* and op_hrfid are to be added here # then additional op-decoding is required, accordingly - yield branch.p.data_i.spr2.eq(simulator.spr['CTR'].value) + yield branch.p.data_i.spr1.eq(simulator.spr['CTR'].value) print(f"cr0: {simulator.crl[0].get_range()}") yield Settle() -- 2.30.2