From 7ff5a9db2d17c384260c2220c9205a7b4891f001 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 16:58:33 +0000
Subject: [PATCH] equiv_opt: pass -D EQUIV when techmapping.

This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
---
 passes/equiv/equiv_opt.cc  | 6 ++++--
 techlibs/ice40/cells_sim.v | 2 ++
 tests/opt/ice40_carry.v    | 3 ---
 tests/opt/opt_lut.ys       | 2 +-
 4 files changed, 7 insertions(+), 6 deletions(-)
 delete mode 100644 tests/opt/ice40_carry.v

diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc
index 68593d301..408afd3e4 100644
--- a/passes/equiv/equiv_opt.cc
+++ b/passes/equiv/equiv_opt.cc
@@ -137,10 +137,12 @@ struct EquivOptPass : public ScriptPass
 
     if ((!techmap_opts.empty() || help_mode) && check_label("techmap", "(only with -map)"))
     {
+      string opts;
       if (help_mode)
-        run("techmap -autoproc -map <filename> ...");
+        opts = " -map <filename> ...";
       else
-        run("techmap -autoproc" + techmap_opts);
+        opts = techmap_opts;
+      run("techmap -D EQUIV -autoproc" + opts);
     }
 
     if (check_label("prove"))
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index e0a07af32..c554c3f35 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -928,6 +928,7 @@ module SB_SPRAM256KA (
 	output reg [15:0] DATAOUT
 );
 `ifndef BLACKBOX
+`ifndef EQUIV
 	reg [15:0] mem [0:16383];
 	wire off = SLEEP || !POWEROFF;
 	integer i;
@@ -954,6 +955,7 @@ module SB_SPRAM256KA (
 		end
 	end
 `endif
+`endif
 endmodule
 
 (* blackbox *)
diff --git a/tests/opt/ice40_carry.v b/tests/opt/ice40_carry.v
deleted file mode 100644
index ed938932a..000000000
--- a/tests/opt/ice40_carry.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module SB_CARRY (output CO, input I0, I1, CI);
-    assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
index f3c1e2822..59b12c351 100644
--- a/tests/opt/opt_lut.ys
+++ b/tests/opt/opt_lut.ys
@@ -1,4 +1,4 @@
 read_verilog opt_lut.v
 synth_ice40
 ice40_unlut
-equiv_opt -map ice40_carry.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
+equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
-- 
2.30.2