From 801790b37ca817089ecbae214340162e6d94ea6a Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Wed, 7 Aug 2019 19:08:55 +0000 Subject: [PATCH] [AArch64] Prefer FPRs over GPRs for CLASTB This patch makes the SVE CLASTB GPR alternative more expensive than the FPR alternative in order to avoid unnecessary cross-file moves. It also fixes the prefix used to print the FPR; only handles 32-bit and 64-bit elements. 2019-08-07 Richard Sandiford gcc/ * config/aarch64/aarch64-sve.md (fold_extract_last_): Disparage the GPR alternative relative to the FPR one. Fix handling of 8-bit and 16-bit FPR values. gcc/testsuite/ * gcc.target/aarch64/sve/clastb_8.c: New test. From-SVN: r274191 --- gcc/ChangeLog | 6 +++++ gcc/config/aarch64/aarch64-sve.md | 4 +-- gcc/testsuite/ChangeLog | 4 +++ .../gcc.target/aarch64/sve/clastb_8.c | 25 +++++++++++++++++++ 4 files changed, 37 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/clastb_8.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 43e53c0a260..31cbd59c4b6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-08-07 Richard Sandiford + + * config/aarch64/aarch64-sve.md (fold_extract_last_): + Disparage the GPR alternative relative to the FPR one. + Fix handling of 8-bit and 16-bit FPR values. + 2019-08-07 Richard Sandiford * config/aarch64/iterators.md (BITWISEV): Delete. diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 3d60afacc25..41c92a01bab 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -3104,7 +3104,7 @@ ;; Set operand 0 to the last active element in operand 3, or to tied ;; operand 1 if no elements are active. (define_insn "fold_extract_last_" - [(set (match_operand: 0 "register_operand" "=r, w") + [(set (match_operand: 0 "register_operand" "=?r, w") (unspec: [(match_operand: 1 "register_operand" "0, 0") (match_operand: 2 "register_operand" "Upl, Upl") @@ -3113,7 +3113,7 @@ "TARGET_SVE" "@ clastb\t%0, %2, %0, %3. - clastb\t%0, %2, %0, %3." + clastb\t%0, %2, %0, %3." ) ;; ------------------------------------------------------------------------- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a53639841a0..dd37b72aeda 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-08-07 Richard Sandiford + + * gcc.target/aarch64/sve/clastb_8.c: New test. + 2019-08-07 Uroš Bizjak PR target/91385 diff --git a/gcc/testsuite/gcc.target/aarch64/sve/clastb_8.c b/gcc/testsuite/gcc.target/aarch64/sve/clastb_8.c new file mode 100644 index 00000000000..d86a428a7fa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/clastb_8.c @@ -0,0 +1,25 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=256 --save-temps" } */ + +#include + +#define TEST_TYPE(TYPE) \ + void \ + test_##TYPE (TYPE *ptr, TYPE *a, TYPE *b, TYPE min_v) \ + { \ + TYPE last = *ptr; \ + for (int i = 0; i < 1024; i++) \ + if (a[i] < min_v) \ + last = b[i]; \ + *ptr = last; \ + } + +TEST_TYPE (uint8_t); +TEST_TYPE (uint16_t); +TEST_TYPE (uint32_t); +TEST_TYPE (uint64_t); + +/* { dg-final { scan-assembler {\tclastb\t(b[0-9]+), p[0-7], \1, z[0-9]+\.b\n} } } */ +/* { dg-final { scan-assembler {\tclastb\t(h[0-9]+), p[0-7], \1, z[0-9]+\.h\n} } } */ +/* { dg-final { scan-assembler {\tclastb\t(s[0-9]+), p[0-7], \1, z[0-9]+\.s\n} } } */ +/* { dg-final { scan-assembler {\tclastb\t(d[0-9]+), p[0-7], \1, z[0-9]+\.d\n} } } */ -- 2.30.2