From 8023f4e3c8207696a3cd7625926f4e2fab0ef709 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 7 Jul 2019 16:57:19 +0100 Subject: [PATCH] clarify if else --- src/ieee754/div_rem_sqrt_rsqrt/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py index 245cd1c6..f87077df 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/core.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py @@ -357,7 +357,7 @@ class DivPipeCoreCalculateStage(Elaboratable): next_compare_rhs = Signal(radix, reset_less=True) l = [] for i in range(radix): - next_flag = pass_flags[i + 1] if i + 1 < radix else 0 + next_flag = pass_flags[i + 1] if (i + 1 < radix) else Const(0) flag = Signal(reset_less=True, name=f"flag{i}") test = Signal(reset_less=True, name=f"test{i}") # XXX TODO: check the width on this -- 2.30.2