From 8027398c0b9fa3e5d4dd88ec8fb74e4ce55a8af2 Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Sun, 10 Oct 2021 12:01:39 +0100 Subject: [PATCH] fixed image size --- docs/learning_nmigen.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/learning_nmigen.mdwn b/docs/learning_nmigen.mdwn index 14e7bffa1..8f21b9b8d 100644 --- a/docs/learning_nmigen.mdwn +++ b/docs/learning_nmigen.mdwn @@ -17,7 +17,9 @@ * nMigen code for counter and testbench here: 1. Create a file called "up_counter.py" containing the 16-bit up counter code from "Implementing a counter" section. + 1. Create a file called "tb_up_counter.py" containing the testbench from "Testing a counter". + 1. To the testbench file, add the import statement for the counter module (better get used to separating your sim/stimulus and module classes from the beginning): from up_counter import UpCounter @@ -56,4 +58,4 @@ 1. Now you can improve your understanding with the nMigen, verilog, and block diagram views side-by-side! -[[!img nmigen_verilog_tb.png ]] \ No newline at end of file +[[!img nmigen_verilog_tb.png size="600x"]] \ No newline at end of file -- 2.30.2