From 802b9c6abff2fe2388f0d778d384d8b0083a755b Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Tue, 19 May 2020 12:06:52 -0400 Subject: [PATCH] Implement 32 bit cntlz and cnttz --- src/soc/fu/logical/main_stage.py | 17 +++++++++++++++-- src/soc/fu/logical/test/test_pipe_caller.py | 2 +- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/logical/main_stage.py b/src/soc/fu/logical/main_stage.py index 96ace02e..5f93d3e6 100644 --- a/src/soc/fu/logical/main_stage.py +++ b/src/soc/fu/logical/main_stage.py @@ -113,9 +113,22 @@ class LogicalMainStage(PipeModBase): XO = self.fields.FormX.XO[0:-1] count_right = Signal(reset_less=True) comb += count_right.eq(XO[-1]) + + cntz_input = Signal(64, reset_less=True) + with m.If(self.i.ctx.op.is_32bit): + with m.If(count_right): + comb += cntz_input.eq(a[0:32][::-1]) + with m.Else(): + comb += cntz_input.eq(a[0:32]) + with m.Else(): + with m.If(count_right): + comb += cntz_input.eq(a[::-1]) + with m.Else(): + comb += cntz_input.eq(a) m.submodules.clz = clz = CLZ(64) - comb += clz.sig_in.eq(Mux(count_right, a[::-1], a)) - comb += o.eq(clz.lz) + comb += clz.sig_in.eq(cntz_input) + comb += o.eq(Mux(self.i.ctx.op.is_32bit, + clz.lz-32, clz.lz)) ###### bpermd ####### # TODO with m.Case(InternalOp.OP_BPERM): - not in microwatt diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index f3760c7c..b4424521 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -124,7 +124,7 @@ class LogicalTestCase(FHDLTestCase): self.run_tst_program(Program(lst), initial_regs) def test_cntz(self): - insns = ["cntlzd", "cnttzd"] + insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"] for i in range(100): choice = random.choice(insns) lst = [f"{choice} 3, 1"] -- 2.30.2