From 80ad71609c45ad9bb4f93c6836487dc0d00f584f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Aug 2022 19:39:05 +0100 Subject: [PATCH] initialise overflow to zero in setvl, unconditionally. add two new CTR-mode/Rc=1 setvl. tests, to confirm that overflow does/does-not occur correctly when CTR is used as input to set VL --- openpower/isa/simplev.mdwn | 2 +- .../decoder/isa/test_caller_setvl.py | 75 +++++++++++++++++++ 2 files changed, 76 insertions(+), 1 deletion(-) diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index 7d60e901..e177b04d 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -26,12 +26,12 @@ SVL-Form Pseudo-code: + overflow <- 0b0 if (vf & (¬vs) & ¬(ms)) = 1 then step <- SVSTATE_NEXT(SVi, 0b0) if _RT != 0 then GPR(_RT) <- [0]*57 || step else - overflow <- 0b0 VLimm <- SVi + 1 # set or get MVL if ms = 1 then MVL <- VLimm[0:6] diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index c6ddffcd..0f25218b 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -367,6 +367,40 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(CR0[CRFields.GT], 0) self.assertEqual(CR0[CRFields.SO], 0) + def test_setvl_ctr_1_rc1(self): + """setvl CTR mode, with Rc=1, testing if VL and MVL are over-ridden + and CR0 set correctly + """ + lst = SVP64Asm(["setvl. 1, 0, 10, 0, 1, 1", + ]) + lst = list(lst) + + # SVSTATE (in this case, VL=2), want to see if these get changed + svstate = SVP64State() + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) + sprs = {'CTR': 5, + } + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, svstate=svstate, + initial_sprs=sprs) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + self.assertEqual(sim.svstate.vl, 5) + self.assertEqual(sim.svstate.maxvl, 10) + print(" gpr1", sim.gpr(1)) + self.assertEqual(sim.gpr(1), SelectableInt(5, 64)) + + CR0 = sim.crl[0] + print(" CR0", bin(CR0.get_range().value)) + self.assertEqual(CR0[CRFields.EQ], 0) + self.assertEqual(CR0[CRFields.LT], 0) + self.assertEqual(CR0[CRFields.GT], 1) + self.assertEqual(CR0[CRFields.SO], 0) + def test_setvl_ctr_1(self): """setvl CTR mode, testing if VL and MVL are over-ridden """ @@ -393,6 +427,47 @@ class DecoderTestCase(FHDLTestCase): print(" gpr1", sim.gpr(1)) self.assertEqual(sim.gpr(1), SelectableInt(5, 64)) + CR0 = sim.crl[0] + print(" CR0", bin(CR0.get_range().value)) + self.assertEqual(CR0[CRFields.EQ], 0) + self.assertEqual(CR0[CRFields.LT], 0) + self.assertEqual(CR0[CRFields.GT], 0) + self.assertEqual(CR0[CRFields.SO], 0) + + def test_setvl_ctr_2_rc1(self): + """setvl Rc=1, CTR large, testing if VL and MVL are over-ridden, + check if CR0.SO gets set + """ + lst = SVP64Asm(["setvl. 1, 0, 10, 0, 1, 1", + ]) + lst = list(lst) + + # SVSTATE (in this case, VL=2), want to see if these get changed + svstate = SVP64State() + svstate.vl = 2 # VL + svstate.maxvl = 2 # MAXVL + print ("SVSTATE", bin(svstate.asint())) + sprs = {'CTR': 0x1000000000, + } + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, svstate=svstate, + initial_sprs=sprs) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + self.assertEqual(sim.svstate.vl, 10) + self.assertEqual(sim.svstate.maxvl, 10) + print(" gpr1", sim.gpr(1)) + self.assertEqual(sim.gpr(1), SelectableInt(10, 64)) + + CR0 = sim.crl[0] + print(" CR0", bin(CR0.get_range().value)) + self.assertEqual(CR0[CRFields.EQ], 0) + self.assertEqual(CR0[CRFields.LT], 0) + self.assertEqual(CR0[CRFields.GT], 1) + self.assertEqual(CR0[CRFields.SO], 1) + def test_setvl_ctr_2(self): """setvl CTR large, testing if VL and MVL are over-ridden """ -- 2.30.2