From 80aec0f006b91b0163c8be94f2450223e6e97a52 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 3 Sep 2019 16:37:59 -0700
Subject: [PATCH] st.ffP from if to assert

---
 passes/pmgen/xilinx_dsp.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 17e05c39c..95105275b 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -59,7 +59,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 		log("  adder %s (%s)\n", log_id(st.postAdd), log_id(st.postAdd->type));
 
 		SigSpec &opmode = cell->connections_.at("\\OPMODE");
-		if (st.ffP && st.postAddMux) {
+		if (st.postAddMux) {
+			log_assert(st.ffP);
 			opmode[4] = st.postAddMux->getPort("\\S");
 			pm.autoremove(st.postAddMux);
 		}
-- 
2.30.2