From 80ba6fe9662823f6cc338521c3a19159c6fb4f14 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Sep 2018 12:13:25 +0100 Subject: [PATCH] add sv_insn_t overloads for rvc registers --- riscv/sv_decode.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h index e80fab0..3433bda 100644 --- a/riscv/sv_decode.h +++ b/riscv/sv_decode.h @@ -34,6 +34,18 @@ public: { return _remap(insn_t::rs2(), fimap & REG_RS2, offs_rs2, cached_rs2); } uint64_t rs3() { return _remap(insn_t::rs3(), fimap & REG_RS3, offs_rs3, cached_rs3); } + uint64_t rvc_rs1 () + { return _remap(insn_t::rvc_rs1(), fimap & REG_RVC_RS1, + offs_rs1, cached_rs1); } + uint64_t rvc_rs1s () + { return _remap(insn_t::rvc_rs1s(), fimap & REG_RVC_RS1S, + offs_rs1, cached_rs1); } + uint64_t rvc_rs2 () + { return _remap(insn_t::rvc_rs2(), fimap & REG_RVC_RS2, + offs_rs2, cached_rs2); } + uint64_t rvc_rs2s () + { return _remap(insn_t::rvc_rs2s(), fimap & REG_RVC_RS2S, + offs_rs2, cached_rs2); } void reset_caches(void) { -- 2.30.2