From 80be5f3ff2a360828b13d3fb367f5abc716a891b Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 23 Jan 2021 21:10:26 +0000
Subject: [PATCH]

---
 openpower/sv/svp64/appendix.mdwn | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 1e6aba652..8df72f367 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -642,5 +642,19 @@ similar to x86 "rex" prefix.
 
 For actual assembler:
 
-    sv.asmcode.mode.vec reg.v/8, src.s/16, pred={maskreg}, spred={maskreg}
-
+    sv.asmcode/mode.vec{N}.ew=8,sw=16,m={pred},sm={pred} reg.v, src.s
+
+For modes:
+
+* pred-result:
+  - pm=lt/gt/le/ge/eq/ne/so/ns OR
+  - pm=RC1 OR pm=~RC1
+* fail-first
+  - ff=lt/gt/le/ge/eq/ne/so/ns OR
+  - ff=RC1 OR pm=~RC1
+* saturation:
+  - sats
+  - satu
+* map-reduce:
+  - mr OR crm: "normal" map-reduce mode or CR-mode
+  - svm: when SUBVL=2/3/4 (vec2/3/4) sub-vector mapreduce is enabled
-- 
2.30.2