From 80d673e5020c48b55b0be6dc70dd2325cc99f3ac Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 27 Apr 2016 12:34:18 +0200 Subject: [PATCH] soc/integration/soc_sdram: always generate L2_SIZE constant --- litex/soc/integration/soc_sdram.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py index c0594f11..da191414 100644 --- a/litex/soc/integration/soc_sdram.py +++ b/litex/soc/integration/soc_sdram.py @@ -68,8 +68,7 @@ class SoCSDRAM(SoCCore): geom_settings.colbits)*sdram_width//8 # XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories. main_ram_size = min(main_ram_size, 256*1024*1024) - if self.l2_size: - self.add_constant("L2_SIZE", self.l2_size) + self.add_constant("L2_SIZE", self.l2_size) # add a Wishbone interface to the DRAM wb_sdram = wishbone.Interface() -- 2.30.2