From 80d9d15f1c4b73ee73172b06fd2c8c55703aea54 Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Tue, 5 Jun 2018 12:15:59 +0300 Subject: [PATCH] reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files --- tests/{simple/reg_wire_error.v => various/reg_wire_error.sv} | 0 tests/various/reg_wire_error.ys | 1 + 2 files changed, 1 insertion(+) rename tests/{simple/reg_wire_error.v => various/reg_wire_error.sv} (100%) create mode 100644 tests/various/reg_wire_error.ys diff --git a/tests/simple/reg_wire_error.v b/tests/various/reg_wire_error.sv similarity index 100% rename from tests/simple/reg_wire_error.v rename to tests/various/reg_wire_error.sv diff --git a/tests/various/reg_wire_error.ys b/tests/various/reg_wire_error.ys new file mode 100644 index 000000000..b9d03155d --- /dev/null +++ b/tests/various/reg_wire_error.ys @@ -0,0 +1 @@ +read_verilog -sv reg_wire_error.sv -- 2.30.2