From 80e8dfe9dead5a034f8e5ae3f92cc60e99de88b6 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Thu, 18 Oct 2018 11:44:38 -0500 Subject: [PATCH] nir: Rename Boolean-related opcodes to include 32 in the name This is a squash of a bunch of individual changes: nir/builder: Generate 32-bit bool opcodes transparently nir/algebraic: Remap Boolean opcodes to the 32-bit variant Use 32-bit opcodes in the NIR producers and optimizations Generated with a little hand-editing and the following sed commands: sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c Use 32-bit opcodes in the NIR back-ends Generated with a little hand-editing and the following sed commands: sed -i 's/nir_op_ball_fequal/nir_op_b32all_fequal/g' **/*.c sed -i 's/nir_op_bany_fnequal/nir_op_b32any_fnequal/g' **/*.c sed -i 's/nir_op_ball_iequal/nir_op_b32all_iequal/g' **/*.c sed -i 's/nir_op_bany_inequal/nir_op_b32any_inequal/g' **/*.c sed -i 's/nir_op_\([fiu]lt\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ge\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]ne\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fiu]eq\)/nir_op_\132/g' **/*.c sed -i 's/nir_op_\([fi]\)ne32g/nir_op_\1neg/g' **/*.c sed -i 's/nir_op_bcsel/nir_op_b32csel/g' **/*.c Reviewed-by: Eric Anholt Reviewed-by: Bas Nieuwenhuizen Tested-by: Bas Nieuwenhuizen --- src/amd/common/ac_nir_to_llvm.c | 22 ++-- src/broadcom/compiler/nir_to_vir.c | 44 +++---- src/compiler/nir/nir.h | 20 +-- src/compiler/nir/nir_algebraic.py | 30 +++++ src/compiler/nir/nir_builder_opcodes_h.py | 39 +++++- src/compiler/nir/nir_loop_analyze.c | 28 ++--- src/compiler/nir/nir_lower_alu_to_scalar.c | 8 +- src/compiler/nir/nir_opcodes.py | 34 +++--- src/compiler/nir/nir_opt_if.c | 2 +- src/compiler/nir/nir_opt_peephole_select.c | 2 +- src/compiler/nir/nir_opt_undef.c | 2 +- src/compiler/spirv/vtn_alu.c | 62 +++++----- src/freedreno/ir3/ir3_compiler_nir.c | 22 ++-- src/gallium/auxiliary/nir/tgsi_to_nir.c | 20 +-- src/gallium/drivers/vc4/vc4_program.c | 40 +++--- src/intel/compiler/brw_fs_nir.cpp | 66 +++++----- .../brw_nir_analyze_boolean_resolves.c | 24 ++-- src/intel/compiler/brw_vec4_nir.cpp | 114 +++++++++--------- 18 files changed, 323 insertions(+), 256 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 73e4d41c3b3..225c930d896 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -681,34 +681,34 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) LLVMTypeOf(src[0]), ""), ""); break; - case nir_op_ilt: + case nir_op_ilt32: result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]); break; - case nir_op_ine: + case nir_op_ine32: result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]); break; - case nir_op_ieq: + case nir_op_ieq32: result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]); break; - case nir_op_ige: + case nir_op_ige32: result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]); break; - case nir_op_ult: + case nir_op_ult32: result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]); break; - case nir_op_uge: + case nir_op_uge32: result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]); break; - case nir_op_feq: + case nir_op_feq32: result = emit_float_cmp(&ctx->ac, LLVMRealOEQ, src[0], src[1]); break; - case nir_op_fne: + case nir_op_fne32: result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]); break; - case nir_op_flt: + case nir_op_flt32: result = emit_float_cmp(&ctx->ac, LLVMRealOLT, src[0], src[1]); break; - case nir_op_fge: + case nir_op_fge32: result = emit_float_cmp(&ctx->ac, LLVMRealOGE, src[0], src[1]); break; case nir_op_fabs: @@ -910,7 +910,7 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) else result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, ""); break; - case nir_op_bcsel: + case nir_op_b32csel: result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]); break; case nir_op_find_lsb: diff --git a/src/broadcom/compiler/nir_to_vir.c b/src/broadcom/compiler/nir_to_vir.c index 484dc050368..167f00750b4 100644 --- a/src/broadcom/compiler/nir_to_vir.c +++ b/src/broadcom/compiler/nir_to_vir.c @@ -506,45 +506,45 @@ ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest, bool cond_invert = false; switch (compare_instr->op) { - case nir_op_feq: + case nir_op_feq32: case nir_op_seq: vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ); break; - case nir_op_ieq: + case nir_op_ieq32: vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ); break; - case nir_op_fne: + case nir_op_fne32: case nir_op_sne: vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHZ); cond_invert = true; break; - case nir_op_ine: + case nir_op_ine32: vir_PF(c, vir_XOR(c, src0, src1), V3D_QPU_PF_PUSHZ); cond_invert = true; break; - case nir_op_fge: + case nir_op_fge32: case nir_op_sge: vir_PF(c, vir_FCMP(c, src1, src0), V3D_QPU_PF_PUSHC); break; - case nir_op_ige: + case nir_op_ige32: vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC); cond_invert = true; break; - case nir_op_uge: + case nir_op_uge32: vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC); cond_invert = true; break; case nir_op_slt: - case nir_op_flt: + case nir_op_flt32: vir_PF(c, vir_FCMP(c, src0, src1), V3D_QPU_PF_PUSHN); break; - case nir_op_ilt: + case nir_op_ilt32: vir_PF(c, vir_MIN(c, src1, src0), V3D_QPU_PF_PUSHC); break; - case nir_op_ult: + case nir_op_ult32: vir_PF(c, vir_SUB(c, src0, src1), V3D_QPU_PF_PUSHC); break; @@ -565,7 +565,7 @@ ntq_emit_comparison(struct v3d_compile *c, struct qreg *dest, vir_uniform_f(c, 1.0), vir_uniform_f(c, 0.0)); break; - case nir_op_bcsel: + case nir_op_b32csel: *dest = vir_SEL(c, cond, ntq_get_alu_src(c, sel_instr, 1), ntq_get_alu_src(c, sel_instr, 2)); @@ -748,22 +748,22 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) case nir_op_sne: case nir_op_sge: case nir_op_slt: - case nir_op_feq: - case nir_op_fne: - case nir_op_fge: - case nir_op_flt: - case nir_op_ieq: - case nir_op_ine: - case nir_op_ige: - case nir_op_uge: - case nir_op_ilt: - case nir_op_ult: + case nir_op_feq32: + case nir_op_fne32: + case nir_op_fge32: + case nir_op_flt32: + case nir_op_ieq32: + case nir_op_ine32: + case nir_op_ige32: + case nir_op_uge32: + case nir_op_ilt32: + case nir_op_ult32: if (!ntq_emit_comparison(c, &result, instr, instr)) { fprintf(stderr, "Bad comparison instruction\n"); } break; - case nir_op_bcsel: + case nir_op_b32csel: result = ntq_emit_bcsel(c, instr, src); break; case nir_op_fcsel: diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index aae8e83db7a..d16eabdec53 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1559,16 +1559,16 @@ static inline bool nir_alu_instr_is_comparison(const nir_alu_instr *instr) { switch (instr->op) { - case nir_op_flt: - case nir_op_fge: - case nir_op_feq: - case nir_op_fne: - case nir_op_ilt: - case nir_op_ult: - case nir_op_ige: - case nir_op_uge: - case nir_op_ieq: - case nir_op_ine: + case nir_op_flt32: + case nir_op_fge32: + case nir_op_feq32: + case nir_op_fne32: + case nir_op_ilt32: + case nir_op_ult32: + case nir_op_ige32: + case nir_op_uge32: + case nir_op_ieq32: + case nir_op_ine32: case nir_op_i2b32: case nir_op_f2b32: case nir_op_inot: diff --git a/src/compiler/nir/nir_algebraic.py b/src/compiler/nir/nir_algebraic.py index c16cadbdc58..9a28421b799 100644 --- a/src/compiler/nir/nir_algebraic.py +++ b/src/compiler/nir/nir_algebraic.py @@ -277,6 +277,34 @@ class Variable(Value): _opcode_re = re.compile(r"(?P~)?(?P\w+)(?:@(?P\d+))?" r"(?P\([^\)]+\))?") +opcode_remap = { + 'flt' : 'flt32', + 'fge' : 'fge32', + 'feq' : 'feq32', + 'fne' : 'fne32', + 'ilt' : 'ilt32', + 'ige' : 'ige32', + 'ieq' : 'ieq32', + 'ine' : 'ine32', + 'ult' : 'ult32', + 'uge' : 'uge32', + + 'ball_iequal2' : 'b32all_iequal2', + 'ball_iequal3' : 'b32all_iequal3', + 'ball_iequal4' : 'b32all_iequal4', + 'bany_inequal2' : 'b32any_inequal2', + 'bany_inequal3' : 'b32any_inequal3', + 'bany_inequal4' : 'b32any_inequal4', + 'ball_fequal2' : 'b32all_fequal2', + 'ball_fequal3' : 'b32all_fequal3', + 'ball_fequal4' : 'b32all_fequal4', + 'bany_fnequal2' : 'b32any_fnequal2', + 'bany_fnequal3' : 'b32any_fnequal3', + 'bany_fnequal4' : 'b32any_fnequal4', + + 'bcsel' : 'b32csel', +} + class Expression(Value): def __init__(self, expr, name_base, varset): Value.__init__(self, expr, name_base, "expression") @@ -286,6 +314,8 @@ class Expression(Value): assert m and m.group('opcode') is not None self.opcode = m.group('opcode') + if self.opcode in opcode_remap: + self.opcode = opcode_remap[self.opcode] self._bit_size = int(m.group('bits')) if m.group('bits') else None self.inexact = m.group('inexact') is not None self.cond = m.group('cond') diff --git a/src/compiler/nir/nir_builder_opcodes_h.py b/src/compiler/nir/nir_builder_opcodes_h.py index 34b8c4371e1..5c38818d4ec 100644 --- a/src/compiler/nir/nir_builder_opcodes_h.py +++ b/src/compiler/nir/nir_builder_opcodes_h.py @@ -27,6 +27,36 @@ template = """\ #define _NIR_BUILDER_OPCODES_ <% +opcode_remap = { + 'flt' : 'flt32', + 'fge' : 'fge32', + 'feq' : 'feq32', + 'fne' : 'fne32', + 'ilt' : 'ilt32', + 'ige' : 'ige32', + 'ieq' : 'ieq32', + 'ine' : 'ine32', + 'ult' : 'ult32', + 'uge' : 'uge32', + + 'ball_iequal2' : 'b32all_iequal2', + 'ball_iequal3' : 'b32all_iequal3', + 'ball_iequal4' : 'b32all_iequal4', + 'bany_inequal2' : 'b32any_inequal2', + 'bany_inequal3' : 'b32any_inequal3', + 'bany_inequal4' : 'b32any_inequal4', + 'ball_fequal2' : 'b32all_fequal2', + 'ball_fequal3' : 'b32all_fequal3', + 'ball_fequal4' : 'b32all_fequal4', + 'bany_fnequal2' : 'b32any_fnequal2', + 'bany_fnequal3' : 'b32any_fnequal3', + 'bany_fnequal4' : 'b32any_fnequal4', + + 'bcsel' : 'b32csel', +} + +opcode_remap32 = { op32 : op for op, op32 in opcode_remap.items() } + def src_decl_list(num_srcs): return ', '.join('nir_ssa_def *src' + str(i) for i in range(num_srcs)) @@ -35,8 +65,15 @@ def src_list(num_srcs): %> % for name, opcode in sorted(opcodes.items()): + % if name in opcode_remap: + <% continue %> + % elif name in opcode_remap32: + <% builder_name = opcode_remap32[name] %> + % else: + <% builder_name = name %> + % endif static inline nir_ssa_def * -nir_${name}(nir_builder *build, ${src_decl_list(opcode.num_inputs)}) +nir_${builder_name}(nir_builder *build, ${src_decl_list(opcode.num_inputs)}) { return nir_build_alu(build, nir_op_${name}, ${src_list(opcode.num_inputs)}); } diff --git a/src/compiler/nir/nir_loop_analyze.c b/src/compiler/nir/nir_loop_analyze.c index 259f02a854e..a82a5113b5e 100644 --- a/src/compiler/nir/nir_loop_analyze.c +++ b/src/compiler/nir/nir_loop_analyze.c @@ -433,26 +433,26 @@ get_iteration(nir_op cond_op, nir_const_value *initial, nir_const_value *step, int32_t iter; switch (cond_op) { - case nir_op_ige: - case nir_op_ilt: - case nir_op_ieq: - case nir_op_ine: { + case nir_op_ige32: + case nir_op_ilt32: + case nir_op_ieq32: + case nir_op_ine32: { int32_t initial_val = initial->i32[0]; int32_t span = limit->i32[0] - initial_val; iter = span / step->i32[0]; break; } - case nir_op_uge: - case nir_op_ult: { + case nir_op_uge32: + case nir_op_ult32: { uint32_t initial_val = initial->u32[0]; uint32_t span = limit->u32[0] - initial_val; iter = span / step->u32[0]; break; } - case nir_op_fge: - case nir_op_flt: - case nir_op_feq: - case nir_op_fne: { + case nir_op_fge32: + case nir_op_flt32: + case nir_op_feq32: + case nir_op_fne32: { float initial_val = initial->f32[0]; float span = limit->f32[0] - initial_val; iter = span / step->f32[0]; @@ -623,10 +623,10 @@ find_trip_count(loop_info_state *state) bool limit_rhs = true; switch (alu->op) { - case nir_op_fge: case nir_op_ige: case nir_op_uge: - case nir_op_flt: case nir_op_ilt: case nir_op_ult: - case nir_op_feq: case nir_op_ieq: - case nir_op_fne: case nir_op_ine: + case nir_op_fge32: case nir_op_ige32: case nir_op_uge32: + case nir_op_flt32: case nir_op_ilt32: case nir_op_ult32: + case nir_op_feq32: case nir_op_ieq32: + case nir_op_fne32: case nir_op_ine32: /* We assume that the limit is the "right" operand */ basic_ind = get_loop_var(alu->src[0].src.ssa, state); diff --git a/src/compiler/nir/nir_lower_alu_to_scalar.c b/src/compiler/nir/nir_lower_alu_to_scalar.c index 7ef032cd164..e406207c3cd 100644 --- a/src/compiler/nir/nir_lower_alu_to_scalar.c +++ b/src/compiler/nir/nir_lower_alu_to_scalar.c @@ -198,10 +198,10 @@ lower_alu_instr_scalar(nir_alu_instr *instr, nir_builder *b) return false; LOWER_REDUCTION(nir_op_fdot, nir_op_fmul, nir_op_fadd); - LOWER_REDUCTION(nir_op_ball_fequal, nir_op_feq, nir_op_iand); - LOWER_REDUCTION(nir_op_ball_iequal, nir_op_ieq, nir_op_iand); - LOWER_REDUCTION(nir_op_bany_fnequal, nir_op_fne, nir_op_ior); - LOWER_REDUCTION(nir_op_bany_inequal, nir_op_ine, nir_op_ior); + LOWER_REDUCTION(nir_op_b32all_fequal, nir_op_feq32, nir_op_iand); + LOWER_REDUCTION(nir_op_b32all_iequal, nir_op_ieq32, nir_op_iand); + LOWER_REDUCTION(nir_op_b32any_fnequal, nir_op_fne32, nir_op_ior); + LOWER_REDUCTION(nir_op_b32any_inequal, nir_op_ine32, nir_op_ior); LOWER_REDUCTION(nir_op_fall_equal, nir_op_seq, nir_op_fand); LOWER_REDUCTION(nir_op_fany_nequal, nir_op_sne, nir_op_for); diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index 5458ddd8198..c89bdeb436a 100644 --- a/src/compiler/nir/nir_opcodes.py +++ b/src/compiler/nir/nir_opcodes.py @@ -430,7 +430,7 @@ def binop_convert(name, out_type, in_type, alg_props, const_expr): def binop(name, ty, alg_props, const_expr): binop_convert(name, ty, ty, alg_props, const_expr) -def binop_compare(name, ty, alg_props, const_expr): +def binop_compare32(name, ty, alg_props, const_expr): binop_convert(name, tbool32, ty, alg_props, const_expr) def binop_horiz(name, out_size, out_type, src1_size, src1_type, src2_size, @@ -550,26 +550,26 @@ binop("frem", tfloat, "", "src0 - src1 * truncf(src0 / src1)") # these integer-aware comparisons return a boolean (0 or ~0) -binop_compare("flt", tfloat, "", "src0 < src1") -binop_compare("fge", tfloat, "", "src0 >= src1") -binop_compare("feq", tfloat, commutative, "src0 == src1") -binop_compare("fne", tfloat, commutative, "src0 != src1") -binop_compare("ilt", tint, "", "src0 < src1") -binop_compare("ige", tint, "", "src0 >= src1") -binop_compare("ieq", tint, commutative, "src0 == src1") -binop_compare("ine", tint, commutative, "src0 != src1") -binop_compare("ult", tuint, "", "src0 < src1") -binop_compare("uge", tuint, "", "src0 >= src1") +binop_compare32("flt32", tfloat, "", "src0 < src1") +binop_compare32("fge32", tfloat, "", "src0 >= src1") +binop_compare32("feq32", tfloat, commutative, "src0 == src1") +binop_compare32("fne32", tfloat, commutative, "src0 != src1") +binop_compare32("ilt32", tint, "", "src0 < src1") +binop_compare32("ige32", tint, "", "src0 >= src1") +binop_compare32("ieq32", tint, commutative, "src0 == src1") +binop_compare32("ine32", tint, commutative, "src0 != src1") +binop_compare32("ult32", tuint, "", "src0 < src1") +binop_compare32("uge32", tuint, "", "src0 >= src1") # integer-aware GLSL-style comparisons that compare floats and ints -binop_reduce("ball_fequal", 1, tbool32, tfloat, "{src0} == {src1}", +binop_reduce("b32all_fequal", 1, tbool32, tfloat, "{src0} == {src1}", "{src0} && {src1}", "{src}") -binop_reduce("bany_fnequal", 1, tbool32, tfloat, "{src0} != {src1}", +binop_reduce("b32any_fnequal", 1, tbool32, tfloat, "{src0} != {src1}", "{src0} || {src1}", "{src}") -binop_reduce("ball_iequal", 1, tbool32, tint, "{src0} == {src1}", +binop_reduce("b32all_iequal", 1, tbool32, tint, "{src0} == {src1}", "{src0} && {src1}", "{src}") -binop_reduce("bany_inequal", 1, tbool32, tint, "{src0} != {src1}", +binop_reduce("b32any_inequal", 1, tbool32, tint, "{src0} != {src1}", "{src0} || {src1}", "{src}") # non-integer-aware GLSL-style comparisons that return 0.0 or 1.0 @@ -756,8 +756,8 @@ triop("fmed3", tfloat, "fmaxf(fminf(fmaxf(src0, src1), src2), fminf(src0, src1)) triop("imed3", tint, "MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1))") triop("umed3", tuint, "MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1))") -opcode("bcsel", 0, tuint, [0, 0, 0], - [tbool32, tuint, tuint], "", "src0 ? src1 : src2") +opcode("b32csel", 0, tuint, [0, 0, 0], + [tbool32, tuint, tuint], "", "src0 ? src1 : src2") # SM5 bfi assembly triop("bfi", tuint32, """ diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c index c21ac9219f0..f5951271e0d 100644 --- a/src/compiler/nir/nir_opt_if.c +++ b/src/compiler/nir/nir_opt_if.c @@ -609,7 +609,7 @@ can_propagate_through_alu(nir_src *src) case nir_op_inot: case nir_op_b2i32: return true; - case nir_op_bcsel: + case nir_op_b32csel: return src == &alu->src[0].src; default: return false; diff --git a/src/compiler/nir/nir_opt_peephole_select.c b/src/compiler/nir/nir_opt_peephole_select.c index ad9d0abec03..6308c8cab12 100644 --- a/src/compiler/nir/nir_opt_peephole_select.c +++ b/src/compiler/nir/nir_opt_peephole_select.c @@ -205,7 +205,7 @@ nir_opt_peephole_select_block(nir_block *block, nir_shader *shader, break; nir_phi_instr *phi = nir_instr_as_phi(instr); - nir_alu_instr *sel = nir_alu_instr_create(shader, nir_op_bcsel); + nir_alu_instr *sel = nir_alu_instr_create(shader, nir_op_b32csel); nir_src_copy(&sel->src[0].src, &if_stmt->condition, sel); /* Splat the condition to all channels */ memset(sel->src[0].swizzle, 0, sizeof sel->src[0].swizzle); diff --git a/src/compiler/nir/nir_opt_undef.c b/src/compiler/nir/nir_opt_undef.c index c26158dab7e..52c1d257e9f 100644 --- a/src/compiler/nir/nir_opt_undef.c +++ b/src/compiler/nir/nir_opt_undef.c @@ -38,7 +38,7 @@ static bool opt_undef_csel(nir_alu_instr *instr) { - if (instr->op != nir_op_bcsel && instr->op != nir_op_fcsel) + if (instr->op != nir_op_b32csel && instr->op != nir_op_fcsel) return false; assert(instr->dest.dest.is_ssa); diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index dc6fedc9129..b04ada92199 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -244,15 +244,15 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b, case SpvOpShiftRightArithmetic: return nir_op_ishr; case SpvOpShiftLeftLogical: return nir_op_ishl; case SpvOpLogicalOr: return nir_op_ior; - case SpvOpLogicalEqual: return nir_op_ieq; - case SpvOpLogicalNotEqual: return nir_op_ine; + case SpvOpLogicalEqual: return nir_op_ieq32; + case SpvOpLogicalNotEqual: return nir_op_ine32; case SpvOpLogicalAnd: return nir_op_iand; case SpvOpLogicalNot: return nir_op_inot; case SpvOpBitwiseOr: return nir_op_ior; case SpvOpBitwiseXor: return nir_op_ixor; case SpvOpBitwiseAnd: return nir_op_iand; - case SpvOpSelect: return nir_op_bcsel; - case SpvOpIEqual: return nir_op_ieq; + case SpvOpSelect: return nir_op_b32csel; + case SpvOpIEqual: return nir_op_ieq32; case SpvOpBitFieldInsert: return nir_op_bitfield_insert; case SpvOpBitFieldSExtract: return nir_op_ibitfield_extract; @@ -264,27 +264,27 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b, * the logical operator to use since they also need to check if operands are * ordered. */ - case SpvOpFOrdEqual: return nir_op_feq; - case SpvOpFUnordEqual: return nir_op_feq; - case SpvOpINotEqual: return nir_op_ine; - case SpvOpFOrdNotEqual: return nir_op_fne; - case SpvOpFUnordNotEqual: return nir_op_fne; - case SpvOpULessThan: return nir_op_ult; - case SpvOpSLessThan: return nir_op_ilt; - case SpvOpFOrdLessThan: return nir_op_flt; - case SpvOpFUnordLessThan: return nir_op_flt; - case SpvOpUGreaterThan: *swap = true; return nir_op_ult; - case SpvOpSGreaterThan: *swap = true; return nir_op_ilt; - case SpvOpFOrdGreaterThan: *swap = true; return nir_op_flt; - case SpvOpFUnordGreaterThan: *swap = true; return nir_op_flt; - case SpvOpULessThanEqual: *swap = true; return nir_op_uge; - case SpvOpSLessThanEqual: *swap = true; return nir_op_ige; - case SpvOpFOrdLessThanEqual: *swap = true; return nir_op_fge; - case SpvOpFUnordLessThanEqual: *swap = true; return nir_op_fge; - case SpvOpUGreaterThanEqual: return nir_op_uge; - case SpvOpSGreaterThanEqual: return nir_op_ige; - case SpvOpFOrdGreaterThanEqual: return nir_op_fge; - case SpvOpFUnordGreaterThanEqual: return nir_op_fge; + case SpvOpFOrdEqual: return nir_op_feq32; + case SpvOpFUnordEqual: return nir_op_feq32; + case SpvOpINotEqual: return nir_op_ine32; + case SpvOpFOrdNotEqual: return nir_op_fne32; + case SpvOpFUnordNotEqual: return nir_op_fne32; + case SpvOpULessThan: return nir_op_ult32; + case SpvOpSLessThan: return nir_op_ilt32; + case SpvOpFOrdLessThan: return nir_op_flt32; + case SpvOpFUnordLessThan: return nir_op_flt32; + case SpvOpUGreaterThan: *swap = true; return nir_op_ult32; + case SpvOpSGreaterThan: *swap = true; return nir_op_ilt32; + case SpvOpFOrdGreaterThan: *swap = true; return nir_op_flt32; + case SpvOpFUnordGreaterThan: *swap = true; return nir_op_flt32; + case SpvOpULessThanEqual: *swap = true; return nir_op_uge32; + case SpvOpSLessThanEqual: *swap = true; return nir_op_ige32; + case SpvOpFOrdLessThanEqual: *swap = true; return nir_op_fge32; + case SpvOpFUnordLessThanEqual: *swap = true; return nir_op_fge32; + case SpvOpUGreaterThanEqual: return nir_op_uge32; + case SpvOpSGreaterThanEqual: return nir_op_ige32; + case SpvOpFOrdGreaterThanEqual: return nir_op_fge32; + case SpvOpFUnordGreaterThanEqual: return nir_op_fge32; /* Conversions: */ case SpvOpQuantizeToF16: return nir_op_fquantize2f16; @@ -413,9 +413,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, } else { nir_op op; switch (src[0]->num_components) { - case 2: op = nir_op_bany_inequal2; break; - case 3: op = nir_op_bany_inequal3; break; - case 4: op = nir_op_bany_inequal4; break; + case 2: op = nir_op_b32any_inequal2; break; + case 3: op = nir_op_b32any_inequal3; break; + case 4: op = nir_op_b32any_inequal4; break; default: vtn_fail("invalid number of components"); } val->ssa->def = nir_build_alu(&b->nb, op, src[0], @@ -430,9 +430,9 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, } else { nir_op op; switch (src[0]->num_components) { - case 2: op = nir_op_ball_iequal2; break; - case 3: op = nir_op_ball_iequal3; break; - case 4: op = nir_op_ball_iequal4; break; + case 2: op = nir_op_b32all_iequal2; break; + case 3: op = nir_op_b32all_iequal3; break; + case 4: op = nir_op_b32all_iequal4; break; default: vtn_fail("invalid number of components"); } val->ssa->def = nir_build_alu(&b->nb, op, src[0], diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index f8155747c52..85f14f354d2 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -458,22 +458,22 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) dst[0]->cat5.type = TYPE_F32; break; break; - case nir_op_flt: + case nir_op_flt32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_LT; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_fge: + case nir_op_fge32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_GE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_feq: + case nir_op_feq32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_EQ; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_fne: + case nir_op_fne32: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_NE; dst[0] = ir3_n2b(b, dst[0]); @@ -586,38 +586,38 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) case nir_op_ushr: dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0); break; - case nir_op_ilt: + case nir_op_ilt32: dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_LT; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_ige: + case nir_op_ige32: dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_GE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_ieq: + case nir_op_ieq32: dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_EQ; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_ine: + case nir_op_ine32: dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_NE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_ult: + case nir_op_ult32: dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_LT; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_uge: + case nir_op_uge32: dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_GE; dst[0] = ir3_n2b(b, dst[0]); break; - case nir_op_bcsel: { + case nir_op_b32csel: { struct ir3_instruction *cond = ir3_b2n(b, src[0]); compile_assert(ctx, bs[1] == bs[2]); /* the boolean condition is 32b even if src[1] and src[2] are diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c index 5524437a048..9be5b9351d2 100644 --- a/src/gallium/auxiliary/nir/tgsi_to_nir.c +++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c @@ -1469,10 +1469,10 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = { [TGSI_OPCODE_ENDSUB] = 0, /* XXX: no function calls */ [TGSI_OPCODE_NOP] = 0, - [TGSI_OPCODE_FSEQ] = nir_op_feq, - [TGSI_OPCODE_FSGE] = nir_op_fge, - [TGSI_OPCODE_FSLT] = nir_op_flt, - [TGSI_OPCODE_FSNE] = nir_op_fne, + [TGSI_OPCODE_FSEQ] = nir_op_feq32, + [TGSI_OPCODE_FSGE] = nir_op_fge32, + [TGSI_OPCODE_FSLT] = nir_op_flt32, + [TGSI_OPCODE_FSNE] = nir_op_fne32, [TGSI_OPCODE_KILL_IF] = 0, @@ -1483,9 +1483,9 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = { [TGSI_OPCODE_IMAX] = nir_op_imax, [TGSI_OPCODE_IMIN] = nir_op_imin, [TGSI_OPCODE_INEG] = nir_op_ineg, - [TGSI_OPCODE_ISGE] = nir_op_ige, + [TGSI_OPCODE_ISGE] = nir_op_ige32, [TGSI_OPCODE_ISHR] = nir_op_ishr, - [TGSI_OPCODE_ISLT] = nir_op_ilt, + [TGSI_OPCODE_ISLT] = nir_op_ilt32, [TGSI_OPCODE_F2U] = nir_op_f2u32, [TGSI_OPCODE_U2F] = nir_op_u2f32, [TGSI_OPCODE_UADD] = nir_op_iadd, @@ -1495,11 +1495,11 @@ static const nir_op op_trans[TGSI_OPCODE_LAST] = { [TGSI_OPCODE_UMIN] = nir_op_umin, [TGSI_OPCODE_UMOD] = nir_op_umod, [TGSI_OPCODE_UMUL] = nir_op_imul, - [TGSI_OPCODE_USEQ] = nir_op_ieq, - [TGSI_OPCODE_USGE] = nir_op_uge, + [TGSI_OPCODE_USEQ] = nir_op_ieq32, + [TGSI_OPCODE_USGE] = nir_op_uge32, [TGSI_OPCODE_USHR] = nir_op_ushr, - [TGSI_OPCODE_USLT] = nir_op_ult, - [TGSI_OPCODE_USNE] = nir_op_ine, + [TGSI_OPCODE_USLT] = nir_op_ult32, + [TGSI_OPCODE_USNE] = nir_op_ine32, [TGSI_OPCODE_SWITCH] = 0, /* not emitted by glsl_to_tgsi.cpp */ [TGSI_OPCODE_CASE] = 0, /* not emitted by glsl_to_tgsi.cpp */ diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c index f8dce1b1dec..b85df172892 100644 --- a/src/gallium/drivers/vc4/vc4_program.c +++ b/src/gallium/drivers/vc4/vc4_program.c @@ -1004,24 +1004,24 @@ ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest, enum qpu_cond cond; switch (compare_instr->op) { - case nir_op_feq: - case nir_op_ieq: + case nir_op_feq32: + case nir_op_ieq32: case nir_op_seq: cond = QPU_COND_ZS; break; - case nir_op_fne: - case nir_op_ine: + case nir_op_fne32: + case nir_op_ine32: case nir_op_sne: cond = QPU_COND_ZC; break; - case nir_op_fge: - case nir_op_ige: - case nir_op_uge: + case nir_op_fge32: + case nir_op_ige32: + case nir_op_uge32: case nir_op_sge: cond = QPU_COND_NC; break; - case nir_op_flt: - case nir_op_ilt: + case nir_op_flt32: + case nir_op_ilt32: case nir_op_slt: cond = QPU_COND_NS; break; @@ -1048,7 +1048,7 @@ ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest, qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0)); break; - case nir_op_bcsel: + case nir_op_b32csel: *dest = qir_SEL(c, cond, ntq_get_alu_src(c, sel_instr, 1), ntq_get_alu_src(c, sel_instr, 2)); @@ -1264,21 +1264,21 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr) case nir_op_sne: case nir_op_sge: case nir_op_slt: - case nir_op_feq: - case nir_op_fne: - case nir_op_fge: - case nir_op_flt: - case nir_op_ieq: - case nir_op_ine: - case nir_op_ige: - case nir_op_uge: - case nir_op_ilt: + case nir_op_feq32: + case nir_op_fne32: + case nir_op_fge32: + case nir_op_flt32: + case nir_op_ieq32: + case nir_op_ine32: + case nir_op_ige32: + case nir_op_uge32: + case nir_op_ilt32: if (!ntq_emit_comparison(c, &result, instr, instr)) { fprintf(stderr, "Bad comparison instruction\n"); } break; - case nir_op_bcsel: + case nir_op_b32csel: result = ntq_emit_bcsel(c, instr, src); break; case nir_op_fcsel: diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 6d70d744002..92ec85a27cc 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1056,10 +1056,10 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) break; } - case nir_op_flt: - case nir_op_fge: - case nir_op_feq: - case nir_op_fne: { + case nir_op_flt32: + case nir_op_fge32: + case nir_op_feq32: + case nir_op_fne32: { fs_reg dest = result; const uint32_t bit_size = nir_src_bit_size(instr->src[0].src); @@ -1068,16 +1068,16 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) brw_conditional_mod cond; switch (instr->op) { - case nir_op_flt: + case nir_op_flt32: cond = BRW_CONDITIONAL_L; break; - case nir_op_fge: + case nir_op_fge32: cond = BRW_CONDITIONAL_GE; break; - case nir_op_feq: + case nir_op_feq32: cond = BRW_CONDITIONAL_Z; break; - case nir_op_fne: + case nir_op_fne32: cond = BRW_CONDITIONAL_NZ; break; default: @@ -1100,12 +1100,12 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) break; } - case nir_op_ilt: - case nir_op_ult: - case nir_op_ige: - case nir_op_uge: - case nir_op_ieq: - case nir_op_ine: { + case nir_op_ilt32: + case nir_op_ult32: + case nir_op_ige32: + case nir_op_uge32: + case nir_op_ieq32: + case nir_op_ine32: { fs_reg dest = result; const uint32_t bit_size = nir_src_bit_size(instr->src[0].src); @@ -1114,18 +1114,18 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) brw_conditional_mod cond; switch (instr->op) { - case nir_op_ilt: - case nir_op_ult: + case nir_op_ilt32: + case nir_op_ult32: cond = BRW_CONDITIONAL_L; break; - case nir_op_ige: - case nir_op_uge: + case nir_op_ige32: + case nir_op_uge32: cond = BRW_CONDITIONAL_GE; break; - case nir_op_ieq: + case nir_op_ieq32: cond = BRW_CONDITIONAL_Z; break; - case nir_op_ine: + case nir_op_ine32: cond = BRW_CONDITIONAL_NZ; break; default: @@ -1178,18 +1178,18 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) case nir_op_fdot2: case nir_op_fdot3: case nir_op_fdot4: - case nir_op_ball_fequal2: - case nir_op_ball_iequal2: - case nir_op_ball_fequal3: - case nir_op_ball_iequal3: - case nir_op_ball_fequal4: - case nir_op_ball_iequal4: - case nir_op_bany_fnequal2: - case nir_op_bany_inequal2: - case nir_op_bany_fnequal3: - case nir_op_bany_inequal3: - case nir_op_bany_fnequal4: - case nir_op_bany_inequal4: + case nir_op_b32all_fequal2: + case nir_op_b32all_iequal2: + case nir_op_b32all_fequal3: + case nir_op_b32all_iequal3: + case nir_op_b32all_fequal4: + case nir_op_b32all_iequal4: + case nir_op_b32any_fnequal2: + case nir_op_b32any_inequal2: + case nir_op_b32any_fnequal3: + case nir_op_b32any_inequal3: + case nir_op_b32any_fnequal4: + case nir_op_b32any_inequal4: unreachable("Lowered by nir_lower_alu_reductions"); case nir_op_fnoise1_1: @@ -1508,7 +1508,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) inst->saturate = instr->dest.saturate; break; - case nir_op_bcsel: + case nir_op_b32csel: if (optimize_frontfacing_ternary(instr, result)) return; diff --git a/src/intel/compiler/brw_nir_analyze_boolean_resolves.c b/src/intel/compiler/brw_nir_analyze_boolean_resolves.c index 4ad26e21103..b1be54d92ac 100644 --- a/src/intel/compiler/brw_nir_analyze_boolean_resolves.c +++ b/src/intel/compiler/brw_nir_analyze_boolean_resolves.c @@ -109,18 +109,18 @@ analyze_boolean_resolves_block(nir_block *block) uint8_t resolve_status; nir_alu_instr *alu = nir_instr_as_alu(instr); switch (alu->op) { - case nir_op_ball_fequal2: - case nir_op_ball_iequal2: - case nir_op_ball_fequal3: - case nir_op_ball_iequal3: - case nir_op_ball_fequal4: - case nir_op_ball_iequal4: - case nir_op_bany_fnequal2: - case nir_op_bany_inequal2: - case nir_op_bany_fnequal3: - case nir_op_bany_inequal3: - case nir_op_bany_fnequal4: - case nir_op_bany_inequal4: + case nir_op_b32all_fequal2: + case nir_op_b32all_iequal2: + case nir_op_b32all_fequal3: + case nir_op_b32all_iequal3: + case nir_op_b32all_fequal4: + case nir_op_b32all_iequal4: + case nir_op_b32any_fnequal2: + case nir_op_b32any_inequal2: + case nir_op_b32any_fnequal3: + case nir_op_b32any_inequal3: + case nir_op_b32any_fnequal4: + case nir_op_b32any_inequal4: /* These are only implemented by the vec4 backend and its * implementation emits resolved booleans. At some point in the * future, this may change and we'll have to remove some of the diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 26dc3110e2c..f8d4dfb4682 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -833,34 +833,34 @@ static enum brw_conditional_mod brw_conditional_for_nir_comparison(nir_op op) { switch (op) { - case nir_op_flt: - case nir_op_ilt: - case nir_op_ult: + case nir_op_flt32: + case nir_op_ilt32: + case nir_op_ult32: return BRW_CONDITIONAL_L; - case nir_op_fge: - case nir_op_ige: - case nir_op_uge: + case nir_op_fge32: + case nir_op_ige32: + case nir_op_uge32: return BRW_CONDITIONAL_GE; - case nir_op_feq: - case nir_op_ieq: - case nir_op_ball_fequal2: - case nir_op_ball_iequal2: - case nir_op_ball_fequal3: - case nir_op_ball_iequal3: - case nir_op_ball_fequal4: - case nir_op_ball_iequal4: + case nir_op_feq32: + case nir_op_ieq32: + case nir_op_b32all_fequal2: + case nir_op_b32all_iequal2: + case nir_op_b32all_fequal3: + case nir_op_b32all_iequal3: + case nir_op_b32all_fequal4: + case nir_op_b32all_iequal4: return BRW_CONDITIONAL_Z; - case nir_op_fne: - case nir_op_ine: - case nir_op_bany_fnequal2: - case nir_op_bany_inequal2: - case nir_op_bany_fnequal3: - case nir_op_bany_inequal3: - case nir_op_bany_fnequal4: - case nir_op_bany_inequal4: + case nir_op_fne32: + case nir_op_ine32: + case nir_op_b32any_fnequal2: + case nir_op_b32any_inequal2: + case nir_op_b32any_fnequal3: + case nir_op_b32any_inequal3: + case nir_op_b32any_fnequal4: + case nir_op_b32any_inequal4: return BRW_CONDITIONAL_NZ; default: @@ -880,20 +880,20 @@ vec4_visitor::optimize_predicate(nir_alu_instr *instr, nir_instr_as_alu(instr->src[0].src.ssa->parent_instr); switch (cmp_instr->op) { - case nir_op_bany_fnequal2: - case nir_op_bany_inequal2: - case nir_op_bany_fnequal3: - case nir_op_bany_inequal3: - case nir_op_bany_fnequal4: - case nir_op_bany_inequal4: + case nir_op_b32any_fnequal2: + case nir_op_b32any_inequal2: + case nir_op_b32any_fnequal3: + case nir_op_b32any_inequal3: + case nir_op_b32any_fnequal4: + case nir_op_b32any_inequal4: *predicate = BRW_PREDICATE_ALIGN16_ANY4H; break; - case nir_op_ball_fequal2: - case nir_op_ball_iequal2: - case nir_op_ball_fequal3: - case nir_op_ball_iequal3: - case nir_op_ball_fequal4: - case nir_op_ball_iequal4: + case nir_op_b32all_fequal2: + case nir_op_b32all_iequal2: + case nir_op_b32all_fequal3: + case nir_op_b32all_iequal3: + case nir_op_b32all_fequal4: + case nir_op_b32all_iequal4: *predicate = BRW_PREDICATE_ALIGN16_ALL4H; break; default: @@ -1340,18 +1340,18 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_fddy_fine: unreachable("derivatives are not valid in vertex shaders"); - case nir_op_ilt: - case nir_op_ult: - case nir_op_ige: - case nir_op_uge: - case nir_op_ieq: - case nir_op_ine: + case nir_op_ilt32: + case nir_op_ult32: + case nir_op_ige32: + case nir_op_uge32: + case nir_op_ieq32: + case nir_op_ine32: assert(nir_dest_bit_size(instr->dest.dest) < 64); /* Fallthrough */ - case nir_op_flt: - case nir_op_fge: - case nir_op_feq: - case nir_op_fne: { + case nir_op_flt32: + case nir_op_fge32: + case nir_op_feq32: + case nir_op_fne32: { enum brw_conditional_mod conditional_mod = brw_conditional_for_nir_comparison(instr->op); @@ -1372,14 +1372,14 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; } - case nir_op_ball_iequal2: - case nir_op_ball_iequal3: - case nir_op_ball_iequal4: + case nir_op_b32all_iequal2: + case nir_op_b32all_iequal3: + case nir_op_b32all_iequal4: assert(nir_dest_bit_size(instr->dest.dest) < 64); /* Fallthrough */ - case nir_op_ball_fequal2: - case nir_op_ball_fequal3: - case nir_op_ball_fequal4: { + case nir_op_b32all_fequal2: + case nir_op_b32all_fequal3: + case nir_op_b32all_fequal4: { unsigned swiz = brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]); @@ -1391,14 +1391,14 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; } - case nir_op_bany_inequal2: - case nir_op_bany_inequal3: - case nir_op_bany_inequal4: + case nir_op_b32any_inequal2: + case nir_op_b32any_inequal3: + case nir_op_b32any_inequal4: assert(nir_dest_bit_size(instr->dest.dest) < 64); /* Fallthrough */ - case nir_op_bany_fnequal2: - case nir_op_bany_fnequal3: - case nir_op_bany_fnequal4: { + case nir_op_b32any_fnequal2: + case nir_op_b32any_fnequal3: + case nir_op_b32any_fnequal4: { unsigned swiz = brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]); @@ -1798,7 +1798,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) inst->saturate = instr->dest.saturate; break; - case nir_op_bcsel: + case nir_op_b32csel: enum brw_predicate predicate; if (!optimize_predicate(instr, &predicate)) { emit(CMP(dst_null_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ)); -- 2.30.2