From 80eaddc33a7e33a32dc9ae96e77a8c54543c1bd3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 27 Apr 2022 14:45:30 +0100 Subject: [PATCH] add divrem2du instruction --- openpower/sv/biginteger.mdwn | 42 +++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn index 1d15f0965..e92ba87d3 100644 --- a/openpower/sv/biginteger.mdwn +++ b/openpower/sv/biginteger.mdwn @@ -70,7 +70,7 @@ used with the additional bit set for determining RS. | Rsrc1\_EXTRA2 | `12:13` | extends RA (R\*\_EXTRA2 Encoding) | | Rsrc2\_EXTRA2 | `14:15` | extends RB (R\*\_EXTRA2 Encoding) | | Rsrc3\_EXTRA2 | `16:17` | extends RC (R\*\_EXTRA2 Encoding) | -| EXTRA2_MODE | `18` | used by `madded` for RS | +| EXTRA2_MODE | `18` | used by `madded` for determining RS | When `EXTRA2_MODE` is set to zero, the implicit RS register takes its Vector/Scalar setting from Rdest_EXTRA2, and takes @@ -82,17 +82,43 @@ When `EXTRA2_MODE` is set to one, the implicit RS register is identical to RC extended to SVP64 numbering, including whether RC is set Scalar or Vector. -# divqdu RT,EA,RB +# divrem2du RT,RA,RB,RC -Divide Quad-Double Extended Unsigned is an XO-Form instruction -that is near-identical to `divdeu` except that the lower -64 bits of the dividend, instead of being zero, contain a second implicit -register, RS. RB, the divisor, remains 64 bit. It is therefore a 128/64 -division, producing a 64 bit result. +**DRAFT** + +Divide/Modulu Quad-Double Unsigned is another VA-Form instruction +that is near-identical to `divdeu` except that: + +* the lower 64 bits of the dividend, instead of being zero, contain a + register, RC. +* it performs a fused divide and modulo in a single instruction, storing + the modulo in an implicit RS (similar to `madded`) + +RB, the divisor, remains 64 bit. The instruction is therefore a 128/64 +division, producing a (pair) of 64 bit result(s). Overflow conditions +are detected in exactly the same fashion as `divdeu`, except that rather +than have `UNDEFINED` behaviour, RT is set to all ones and RS set to all +zeros. + +For SVP64, given that this instruction is also 3-in 2-out 64-bit registers, +the exact same EXTRA format and setting of RS is used as for `sv.madded`. +For Scalar usage, just as for `madded`, `RS=RT+1` (similar to `lq` and `stq`). Pseudo-code: - dividend[0:(XLEN*2)-1] <- (RA) || (RS) + if ((RA)