From 80ee74f16cccf23480a7eb8aa43ed3f155151cbe Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 23 May 2020 19:12:06 +0100 Subject: [PATCH] document purpose of regspec module --- src/soc/fu/regspec.py | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py index 31931f57..4e6fc5d1 100644 --- a/src/soc/fu/regspec.py +++ b/src/soc/fu/regspec.py @@ -1,4 +1,22 @@ -# see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs +"""RegSpecs + +see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs + +this module is a key strategic module that links pipeline specifications +(soc.fu.*.pipe_data and soc.fo.*.pipeline) to MultiCompUnits. MultiCompUnits +know absolutely nothing about the data passing through them: all they know +is: how many inputs they need to manage, and how many outputs. + +regspecs tell MultiCompUnit what the ordering of the inputs is, how many to +create, and how to connect them up to the ALU being "managed" by this CompUnit. +likewise for outputs. + +later (TODO) the Register Files will be connected to MultiCompUnits, and, +again, the regspecs will say which Regfile (which type) is connected to +which MultiCompUnit port, how wide the connection is, and so on. + +""" + def get_regspec_bitwidth(regspec, srcdest, idx): bitspec = regspec[srcdest][idx] -- 2.30.2