From 80fbef229a74420ab5708c32432938cedfbc5e0b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 28 Jan 2021 15:53:50 +0000 Subject: [PATCH] add SVState SPR Record, SVSTATERec --- src/soc/sv/svstate.py | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 src/soc/sv/svstate.py diff --git a/src/soc/sv/svstate.py b/src/soc/sv/svstate.py new file mode 100644 index 00000000..7307ce60 --- /dev/null +++ b/src/soc/sv/svstate.py @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: LGPLv3+ +# Copyright (C) 2021 Luke Kenneth Casson Leighton +# Funded by NLnet http://nlnet.nl +"""SVSATE SPR Record. actually a peer of PC (CIA/NIA) and MSR + +https://libre-soc.org/openpower/sv/sprs/ + +| Field | Name | Description | +| ----- | -------- | --------------------- | +| 0:6 | maxvl | Max Vector Length | +| 7:13 | vl | Vector Length | +| 14:20 | srcstep | for srcstep = 0..VL-1 | +| 21:27 | dststep | for dststep = 0..VL-1 | +| 28:29 | subvl | Sub-vector length | +| 30:31 | svstep | for svstep = 0..SUBVL-1 | +""" + +from nmigen import Record + +class SVSTATERec(Record): + def __init__(self, name=None): + Record.__init__([("maxvl" : 8), + ("vl" : 7), + ("srcstep" : 7), + ("dststep" : 7), + ("subvl" : 2), + ("svstep" : 2), name=name) + -- 2.30.2