From 81061d3001d75c481013a242667ce27658b502d9 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 27 Mar 2020 17:28:26 -0700 Subject: [PATCH] arm: Teach gem5 to recognize the gem5 semihosting immediate values. These give access to the gem5 extension calls, currently only the pseudo ops. Change-Id: I60ece82f1f084791971a2de0b54be2f0d9da243e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27246 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com> --- src/arch/arm/isa/includes.isa | 1 + src/arch/arm/isa/insts/misc.isa | 10 +++++++--- src/arch/arm/isa/insts/misc64.isa | 5 ++++- src/arch/arm/semihosting.hh | 11 +++++++++++ 4 files changed, 23 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa index 9cdc1f926..14d1c5572 100644 --- a/src/arch/arm/isa/includes.isa +++ b/src/arch/arm/isa/includes.isa @@ -98,6 +98,7 @@ output exec {{ #include "arch/arm/isa.hh" #include "arch/arm/isa_traits.hh" #include "arch/arm/pauth_helpers.hh" +#include "arch/arm/semihosting.hh" #include "arch/arm/utility.hh" #include "arch/generic/memhelpers.hh" #include "base/condcodes.hh" diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index e8935b842..b2f459158 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -40,10 +40,14 @@ let {{ svcCode = ''' ThreadContext *tc = xc->tcBase(); - const auto semihost_imm = Thumb? 0xAB : 0x123456; - - if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) { + bool have_semi = ArmSystem::haveSemihosting(tc); + if (have_semi && Thumb && imm == ArmSemihosting::T32Imm) { + // Enable gem5 extensions since we can't distinguish in thumb. + ArmSystem::callSemihosting32(tc, true); + } else if (have_semi && imm == ArmSemihosting::A32Imm) { ArmSystem::callSemihosting32(tc); + } else if (have_semi && imm == ArmSemihosting::Gem5Imm) { + ArmSystem::callSemihosting32(tc, true); } else { fault = std::make_shared(machInst, imm); } diff --git a/src/arch/arm/isa/insts/misc64.isa b/src/arch/arm/isa/insts/misc64.isa index e2cfb41dd..656a23445 100644 --- a/src/arch/arm/isa/insts/misc64.isa +++ b/src/arch/arm/isa/insts/misc64.isa @@ -185,8 +185,11 @@ let {{ hltCode = ''' ThreadContext *tc = xc->tcBase(); - if (ArmSystem::haveSemihosting(tc) && imm == 0xF000) { + bool have_semi = ArmSystem::haveSemihosting(tc); + if (imm == ArmSemihosting::A64Imm && have_semi) { ArmSystem::callSemihosting64(tc); + } else if (imm == ArmSemihosting::Gem5Imm && have_semi) { + ArmSystem::callSemihosting64(tc, true); } else { // HLT instructions aren't implemented, so treat them as undefined // instructions. diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh index 83d41fd42..e9dc984e2 100644 --- a/src/arch/arm/semihosting.hh +++ b/src/arch/arm/semihosting.hh @@ -73,6 +73,17 @@ class ArmSemihosting : public SimObject { public: + enum { + // Standard ARM immediate values which trigger semihosting. + T32Imm = 0xAB, + A32Imm = 0x123456, + A64Imm = 0xF000, + + // The immediate value which enables gem5 semihosting calls. Use the + // standard value for thumb. + Gem5Imm = 0x5D57 + }; + static PortProxy &portProxy(ThreadContext *tc); struct AbiBase -- 2.30.2