From 810e40da6345a0e8659bd951d16cc5f99ee8bfdd Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Tue, 18 May 2021 19:16:27 +0200 Subject: [PATCH] periph.base: use bridge granularity as CSR bus data width. --- lambdasoc/periph/base.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lambdasoc/periph/base.py b/lambdasoc/periph/base.py index 84c3452..b023ad5 100644 --- a/lambdasoc/periph/base.py +++ b/lambdasoc/periph/base.py @@ -313,7 +313,7 @@ class PeripheralBridge(Elaboratable): for bank, bank_addr, bank_alignment in periph.iter_csr_banks(): if bank_alignment is None: bank_alignment = alignment - csr_mux = csr.Multiplexer(addr_width=1, data_width=8, alignment=bank_alignment) + csr_mux = csr.Multiplexer(addr_width=1, data_width=granularity, alignment=bank_alignment) for elem, elem_addr, elem_alignment in bank.iter_csr_regs(): if elem_alignment is None: elem_alignment = alignment -- 2.30.2