From 810f03298aa47dae5e427cc794f912bd15305681 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 11 May 2019 05:12:38 +0100 Subject: [PATCH] add a jk latch (as a comment), TODO --- src/nmutil/latch.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py index a334f667..d845a954 100644 --- a/src/nmutil/latch.py +++ b/src/nmutil/latch.py @@ -2,6 +2,24 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil from nmigen import Signal, Module, Elaboratable +""" jk latch + +module jk(q,q1,j,k,c); +output q,q1; +input j,k,c; +reg q,q1; +initial begin q=1'b0; q1=1'b1; end +always @ (posedge c) + begin + case({j,k}) + {1'b0,1'b0}:begin q=q; q1=q1; end + {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end + {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end + {1'b1,1'b1}: begin q=~q; q1=~q1; end + endcase + end +endmodule +""" class SRLatch(Elaboratable): def __init__(self, sync=True): -- 2.30.2