From 8131b94ccd782c6e5c303869c5e34c2af41bebb6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 5 Jun 2019 06:22:55 +0100 Subject: [PATCH] add addrgen comment --- src/scoreboard/addr_match.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/scoreboard/addr_match.py b/src/scoreboard/addr_match.py index 657f95b6..3edbdfeb 100644 --- a/src/scoreboard/addr_match.py +++ b/src/scoreboard/addr_match.py @@ -19,6 +19,13 @@ without using expensive comparators) probably the best way to do so would be to turn the last 16 bits into a byte-level bitmap. LD/ST on a byte would have 1 of the 16 bits set. LD/ST on a DWORD would have 8 of the 16 bits set (offset if the LD/ST was misaligned). TODO. + +Notes: + +> I have used bits <11:6> as they are not translated (4KB pages) +> and larger than a cache line (64 bytes). +> I have used bits <11:4> when the L1 cache was QuadW sized and +> the L2 cache was Line sized. """ from nmigen.compat.sim import run_simulation -- 2.30.2