From 814049be46390dc4fb5c938abf13619b38e696d8 Mon Sep 17 00:00:00 2001 From: Walter Lee Date: Sat, 19 Nov 2016 02:30:41 +0000 Subject: [PATCH] TILE-Gx: fix clzsi2 for big-endian. * config/tilegx/tilegx.md (clzsi2): Fix for big-endian. From-SVN: r242616 --- gcc/ChangeLog | 4 ++++ gcc/config/tilegx/tilegx.md | 27 ++++++++++++++------------- 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 67938695608..13b60c2e1e8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2016-11-18 Walter Lee + + * config/tilegx/tilegx.md (clzsi2): Fix for big-endian. + 2016-11-18 Jakub Jelinek PR middle-end/78419 diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md index 361d51c6756..55c345c50d4 100644 --- a/gcc/config/tilegx/tilegx.md +++ b/gcc/config/tilegx/tilegx.md @@ -1798,19 +1798,20 @@ [(set_attr "type" "Y0")]) (define_expand "clzsi2" - [(set (match_dup 2) - (zero_extend:DI (match_operand:SI 1 "reg_or_0_operand" ""))) - (set (match_dup 2) - (ashift:DI (match_dup 2) - (const_int 32))) - (set (match_dup 2) - (clz:DI (match_dup 2))) - (set (match_operand:SI 0 "register_operand" "") - (subreg:SI (match_dup 2) 0))] - "" - { - operands[2] = gen_reg_rtx (DImode); - }) + [(set (match_operand:SI 0 "register_operand" "=r") + (clz:SI (match_operand:SI 1 "reg_or_0_operand" "rO")))] + "" + { + rtx tmp1 = gen_reg_rtx (DImode); + rtx tmp2 = gen_reg_rtx (DImode); + rtx tmp3 = gen_reg_rtx (DImode); + + emit_insn (gen_zero_extendsidi2 (tmp1, operands[1])); + emit_insn (gen_ashldi3 (tmp2, tmp1, (GEN_INT (32)))); + emit_insn (gen_clzdi2 (tmp3, tmp2)); + emit_move_insn (operands[0], gen_lowpart (SImode, tmp3)); + DONE; + }) (define_insn "ctz2" [(set (match_operand:I48MODE 0 "register_operand" "=r") -- 2.30.2