From 8143f1a08bbe8cf6f85eb6ef74583f4ec8f864c9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 17 Jul 2020 11:56:27 +0200 Subject: [PATCH] soc/cores/spi: make sure miso is stable during xfer. --- litex/soc/cores/spi.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/spi.py b/litex/soc/cores/spi.py index 9ed595a1..c495c58b 100644 --- a/litex/soc/cores/spi.py +++ b/litex/soc/cores/spi.py @@ -113,7 +113,7 @@ class SPIMaster(Module, AutoCSR): # Master In Slave Out (MISO) capture (captured on spi_clk rising edge) -------------------- miso = Signal() - miso_data = self.miso + miso_data = Signal(data_width) self.sync += [ If(clk_rise & shift, If(self.loopback, @@ -124,7 +124,8 @@ class SPIMaster(Module, AutoCSR): ), If(clk_fall & shift, miso_data.eq(Cat(miso, miso_data)) - ) + ), + If(self.done, self.miso.eq(miso_data)), ] def add_csr(self, with_cs=True, with_loopback=True): -- 2.30.2