From 8159b65bee8d32a463dc97f9c1ca1e9b40f63782 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 10 Apr 2020 10:25:21 +0200 Subject: [PATCH] litex/build/io: also import CRG (since using DifferentialInput). --- litex/boards/targets/netv2.py | 5 ++--- litex/boards/targets/simple.py | 3 ++- litex/build/generic_platform.py | 2 +- litex/build/io.py | 23 ++++++++++++++++++++++- 4 files changed, 27 insertions(+), 6 deletions(-) diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index 5ac6b230..cb427048 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -20,9 +20,6 @@ from litedram.phy import s7ddrphy from liteeth.phy.rmii import LiteEthPHYRMII -from litespi import LiteSPI -from litespi.phy.generic import LiteSPIPHY - # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): @@ -78,6 +75,8 @@ class BaseSoC(SoCCore): # SPI XIP ---------------------------------------------------------------------------------- if with_spi_xip: + from litespi import LiteSPI + from litespi.phy.generic import LiteSPIPHY spi_xip_size = 1024*1024*8 self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x")) self.submodules.spictl = LiteSPI(phy=self.spiphy, endianness=self.cpu.endianness) diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index b7befc89..b208544f 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -8,7 +8,8 @@ import argparse import importlib from migen import * -from migen.genlib.io import CRG + +from litex.build.io import CRG from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * diff --git a/litex/build/generic_platform.py b/litex/build/generic_platform.py index 65d70665..d540cc38 100644 --- a/litex/build/generic_platform.py +++ b/litex/build/generic_platform.py @@ -7,10 +7,10 @@ import os from migen.fhdl.structure import Signal from migen.genlib.record import Record -from migen.genlib.io import CRG from litex.gen.fhdl import verilog +from litex.build.io import CRG from litex.build import tools diff --git a/litex/build/io.py b/litex/build/io.py index 690477a9..a052973c 100644 --- a/litex/build/io.py +++ b/litex/build/io.py @@ -1,4 +1,5 @@ # This file is Copyright (c) 2015-2020 Florent Kermarrec +# This file is Copyright (c) 2015 Sebastien Bourdeauducq # License: BSD from migen import * @@ -39,7 +40,6 @@ class DifferentialOutput(Special): def lower(dr): raise NotImplementedError("Attempted to use a Differential Output, but platform does not support them") - # SDR Input/Output --------------------------------------------------------------------------------- class InferedSDRIO(Module): @@ -111,3 +111,24 @@ class DDROutput(Special): @staticmethod def lower(dr): raise NotImplementedError("Attempted to use a DDR output, but platform does not support them") + +# Clock Reset Generator ---------------------------------------------------------------------------- + +class CRG(Module): + def __init__(self, clk, rst=0): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_por = ClockDomain(reset_less=True) + + if hasattr(clk, "p"): + clk_se = Signal() + self.specials += DifferentialInput(clk.p, clk.n, clk_se) + clk = clk_se + + # Power on Reset (vendor agnostic) + int_rst = Signal(reset=1) + self.sync.por += int_rst.eq(rst) + self.comb += [ + self.cd_sys.clk.eq(clk), + self.cd_por.clk.eq(clk), + self.cd_sys.rst.eq(int_rst) + ] -- 2.30.2