From 81a8f3a47e70a26ddb71f18c12c7b2d28de20468 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 4 Jul 2019 17:47:06 +0100 Subject: [PATCH] --- simple_v_extension/vblock_format.mdwn | 2 ++ 1 file changed, 2 insertions(+) diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn index cf5c0f9e8..57d823edc 100644 --- a/simple_v_extension/vblock_format.mdwn +++ b/simple_v_extension/vblock_format.mdwn @@ -57,6 +57,8 @@ As there are not very many bits available without going into a prefix format lon Also, the number of entries in each table is specified with an unusual encoding, on the basis that if registers are to be Vectorised, it is highly likely that they will be predicated as well. +The VL Block is optional and also only 16 bits: this because an RVC opcode is limited by comparison. + The format is explained as follows: * Bit 7 specifies if the register prefix block format is the full 16 bit format -- 2.30.2