From 81b9e12b23cdaf688f2d0bbfb40c0ea7d9a6f890 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 9 May 2022 00:07:33 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index c81a50425..c0cff4b7f 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -887,7 +887,9 @@ Horizontal-First Mode is the standard Cray-Style Vectorisation: loop on all elements with the same instruction before moving on to the next instruction. Predication needs to be pre-calculated for the entire Vector in order to exclude certain elements from -the computation. In this case, that's an expensive inconvenience. +the computation. In this case, that's an expensive inconvenience +(similar to the problems associated with Memory-to-Memory +Vector Machines such as the CDC Star-100). Vertical-First allows *scalar* temporary registers to be utilised in the assessment as to whether a particular Vector element should @@ -897,13 +899,13 @@ to MyISA 66000. Careful analysis of the registers within the Vertical-First Loop allows a Multi-Issue Out-of-Order Engine to *amortise in-flight scalar looped operations into SIMD batches* as long as the loop is kept small enough to entirely fit into -in-flight Reservation Stations. +in-flight Reservation Stations in the first place. *
(With thanks and gratitude to Mitch Alsup on comp.arch for spending considerable time explaining VVM, how its Loop Construct explicitly identifies loop-invariant registers, -and how to exploit GB-OoO Micro-architectures) +and how that helps to exploit a GB-OoO Micro-architectures)
* **Use-case: More powerful in-memory PEs** -- 2.30.2