From 81e8161ab8656d1611493c323d319a03c4da748e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 17 Aug 2022 17:18:09 +0100 Subject: [PATCH] again part of the removal of LD/ST-with-shift, take out the early detection of a LD/ST operation that was formerly needed for the SVP64.RM decoding to use a completely different 32-bit encoding. we established with the whole LD/ST-with-shift experiment that this was a really, really bad idea --- src/openpower/decoder/power_decoder2.py | 24 +++--------------------- 1 file changed, 3 insertions(+), 21 deletions(-) diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index f2c4a0f6..fc1d35b0 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1029,27 +1029,7 @@ class PowerDecodeSubset(Elaboratable): # the alternative decoder, svdecldst. what a mess... *sigh* sv_ptype = self.op_get("SV_Ptype") fn = self.op_get("function_unit") - # detect major opcode for LDs: include 58 here. from CSV files. - # BLECH! TODO: these should be done using "mini decoders", - # using row and column subsets - is_major_ld = Signal() - # bits... errr... MSB0 0..5 which is 26:32 python - major = Signal(6) - comb += major.eq(self.dec.opcode_in[26:32]) - comb += is_major_ld.eq((major == 34) | (major == 35) | - (major == 50) | (major == 51) | - (major == 48) | (major == 49) | - (major == 42) | (major == 43) | - (major == 40) | (major == 41) | - (major == 32) | (major == 33) | - (major == 58)) - with m.If(self.is_svp64_mode & is_major_ld): - # straight-up: "it's a LD". this gives enough info - # for SVP64 RM Mode decoding to detect LD/ST, and - # consequently detect the SHIFT mode. sigh - comb += rm_dec.fn_in.eq(Function.LDST) - with m.Else(): - comb += rm_dec.fn_in.eq(fn) # decode needs to know Fn type + comb += rm_dec.fn_in.eq(fn) # decode needs to know Fn type comb += rm_dec.ptype_in.eq(sv_ptype) # Single/Twin predicated comb += rm_dec.rc_in.eq(rc_out) # Rc=1 comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode @@ -1062,6 +1042,8 @@ class PowerDecodeSubset(Elaboratable): # exclude fcfids and others # XXX this is a REALLY bad hack, REALLY has to be done better. # likely with a sub-decoder. + major = Signal(6) + comb += major.eq(self.dec.opcode_in[26:32]) xo5 = Signal(1) # 1 bit from Minor 59 XO field == 0b0XXXX comb += xo5.eq(self.dec.opcode_in[5]) xo = Signal(5) # 5 bits from Minor 59 fcfids == 0b01110 -- 2.30.2