From 820b2fdd65c4022b555b440beabc65b123421090 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 2 Feb 2022 09:37:32 +0100 Subject: [PATCH] added stimulus mode and param check --- passes/sat/sim.cc | 36 +++++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index c6fc1518f..bb1b1dfa3 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -29,6 +29,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN enum class SimulationMode { + sim, cmp, gold, gate, @@ -73,7 +74,7 @@ struct SimShared FstData *fst = nullptr; double start_time = 0; double stop_time = -1; - SimulationMode sim_mode = SimulationMode::cmp; + SimulationMode sim_mode = SimulationMode::sim; bool cycles_set = false; }; @@ -746,7 +747,9 @@ struct SimInstance Const sim_val = get_state(item.first); if (sim_val.size()!=fst_val.size()) log_error("Signal '%s' size is different in gold and gate.\n", log_id(item.first)); - if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X + if (shared->sim_mode == SimulationMode::sim) { + // No checks performed when using stimulus + } else if (shared->sim_mode == SimulationMode::gate && !fst_val.is_fully_def()) { // FST data contains X for(int i=0;i\n"); - log(" number of cycles to simulate (default: 20)\n"); + log(" number of clock cycles to simulate (default: 20)\n"); log("\n"); log(" -a\n"); - log(" include all nets in VCD output, not just those with public names\n"); + log(" use all nets in VCD/FST operations, not just those with public names\n"); log("\n"); log(" -w\n"); log(" writeback mode: use final simulation state as new init state\n"); @@ -1123,14 +1126,20 @@ struct SimPass : public Pass { log(" -scope\n"); log(" scope of simulation top model\n"); log("\n"); + log(" -at