From 82545236fe16a9947d8871848cda26f38c106ab5 Mon Sep 17 00:00:00 2001 From: klehman Date: Sat, 18 Sep 2021 07:42:22 -0400 Subject: [PATCH] added get_mem and compare_mem --- src/openpower/test/state.py | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/openpower/test/state.py b/src/openpower/test/state.py index aa3aa81f..853da604 100644 --- a/src/openpower/test/state.py +++ b/src/openpower/test/state.py @@ -32,6 +32,7 @@ class State: yield from self.get_crregs() yield from self.get_xregs() yield from self.get_pc() + yield from self.get_mem() def compare(self, s2): # Compare int registers @@ -65,6 +66,13 @@ class State: self.dut.assertEqual(self.pc, s2.pc, "pc mismatch (%s != %s) %s" % (self.state_type, s2.state_type, repr(self.code))) + def compare_mem(self, s2): + for i, (self.mem, s2.mem) in enumerate( + zip(self.mem, s2.mem)): + self.dut.assertEqual(self.mem, s2.mem, + "mem mismatch %s %d %s %s" % (self.code, i, + self.mem, s2.mem)) + class SimState(State): def __init__(self, sim): @@ -110,6 +118,15 @@ class SimState(State): self.pcl.append(self.pc) log("class sim pc", hex(self.pc)) + def get_mem(self): + if False: + yield + keys = list(self.sim.mem.mem.keys()) + self.mem = [] + for k in keys: + if self.sim.mem.mem[k] !=0: # Don't store potential 0 for compare + self.mem.append(((k*8), self.sim.mem.mem[k])) + class ExpectedState(State): def __init__(self, int_regs=None, pc=0, crregs=None, @@ -137,6 +154,8 @@ class ExpectedState(State): if False: yield def get_pc(self): if False: yield + def get_mem(self): + if False: yield global state_factory -- 2.30.2