From 82548a3acac29cc0fcf492a7dc743bedb11e2df2 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Wed, 29 Jul 2015 21:24:20 -0700 Subject: [PATCH] vk/cmd_buffer: Invalidate texture cache in emit_state_base_address Previously, the caller of emit_state_base_address was doing this. However, putting it directly in emit_state_base_address means that we'll never forget the flush at the cost of one PIPE_CONTROL at the top every batch (that should do nothing since the kernel just flushed for us). --- src/vulkan/anv_cmd_emit.c | 80 +++++++++++++++++++-------------------- 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/src/vulkan/anv_cmd_emit.c b/src/vulkan/anv_cmd_emit.c index 93ffb8cf2c1..62b3cda6cd7 100644 --- a/src/vulkan/anv_cmd_emit.c +++ b/src/vulkan/anv_cmd_emit.c @@ -162,6 +162,46 @@ anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer) .InstructionBaseAddressModifyEnable = true, .InstructionBufferSize = 0xfffff, .InstructionBuffersizeModifyEnable = true); + + /* After re-setting the surface state base address, we have to do some + * cache flusing so that the sampler engine will pick up the new + * SURFACE_STATE objects and binding tables. From the Broadwell PRM, + * Shared Function > 3D Sampler > State > State Caching (page 96): + * + * Coherency with system memory in the state cache, like the texture + * cache is handled partially by software. It is expected that the + * command stream or shader will issue Cache Flush operation or + * Cache_Flush sampler message to ensure that the L1 cache remains + * coherent with system memory. + * + * [...] + * + * Whenever the value of the Dynamic_State_Base_Addr, + * Surface_State_Base_Addr are altered, the L1 state cache must be + * invalidated to ensure the new surface or sampler state is fetched + * from system memory. + * + * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit + * which, according the PIPE_CONTROL instruction documentation in the + * Broadwell PRM: + * + * Setting this bit is independent of any other bit in this packet. + * This bit controls the invalidation of the L1 and L2 state caches + * at the top of the pipe i.e. at the parsing time. + * + * Unfortunately, experimentation seems to indicate that state cache + * invalidation through a PIPE_CONTROL does nothing whatsoever in + * regards to surface state and binding tables. In stead, it seems that + * invalidating the texture cache is what is actually needed. + * + * XXX: As far as we have been able to determine through + * experimentation, shows that flush the texture cache appears to be + * sufficient. The theory here is that all of the sampling/rendering + * units cache the binding table in the texture cache. However, we have + * yet to be able to actually confirm this. + */ + anv_batch_emit(&cmd_buffer->batch, GEN8_PIPE_CONTROL, + .TextureCacheInvalidationEnable = true); } VkResult anv_BeginCommandBuffer( @@ -587,46 +627,6 @@ flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer) */ anv_cmd_buffer_emit_state_base_address(cmd_buffer); - /* After re-setting the surface state base address, we have to do - * some cache flusing so that the sampler engine will pick up the new - * SURFACE_STATE objects and binding tables. From the Broadwell PRM, - * Shared Function > 3D Sampler > State > State Caching (page 96): - * - * Coherency with system memory in the state cache, like the - * texture cache is handled partially by software. It is expected - * that the command stream or shader will issue Cache Flush - * operation or Cache_Flush sampler message to ensure that the L1 - * cache remains coherent with system memory. - * - * [...] - * - * Whenever the value of the Dynamic_State_Base_Addr, - * Surface_State_Base_Addr are altered, the L1 state cache must be - * invalidated to ensure the new surface or sampler state is - * fetched from system memory. - * - * The PIPE_CONTROL command has a "State Cache Invalidation Enable" - * bit which, according the PIPE_CONTROL instruction documentation in - * the Broadwell PRM: - * - * Setting this bit is independent of any other bit in this - * packet. This bit controls the invalidation of the L1 and L2 - * state caches at the top of the pipe i.e. at the parsing time. - * - * Unfortunately, experimentation seems to indicate that state cache - * invalidation through a PIPE_CONTROL does nothing whatsoever in - * regards to surface state and binding tables. In stead, it seems - * that invalidating the texture cache is what is actually needed. - * - * XXX: As far as we have been able to determine through - * experimentation, shows that flush the texture cache appears to be - * sufficient. The theory here is that all of the sampling/rendering - * units cache the binding table in the texture cache. However, we - * have yet to be able to actually confirm this. - */ - anv_batch_emit(&cmd_buffer->batch, GEN8_PIPE_CONTROL, - .TextureCacheInvalidationEnable = true); - /* Re-emit all active binding tables */ for_each_bit(s, cmd_buffer->state.pipeline->active_stages) { result = flush_descriptor_set(cmd_buffer, s); -- 2.30.2