From 825b89f8e5502f0ea6693dbb2f13c0c289dd1190 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 3 Nov 2018 08:01:58 +0000 Subject: [PATCH] add debug on zeroing-predication c.mv --- riscv/insn_template_sv.cc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index 1b3ca4f..d235ce3 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -230,6 +230,13 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc) #ifndef INSN_TYPE_C_STACK_ST // XXX TODO: stack-based DEST_REG reg_spec_t rdr = insn._DEST_REG(); bool dest_predicated = (dest_pred & (1<<*dest_offs)) != 0; +#ifdef INSN_C_MV + fprintf(stderr, "post %s %x doffs %lx dp %x zeroing %d tozero %d" \ + " rdr %d v %x\n", + xstr(INSN), INSNCODE, + dest_pred, *dest_offs, zeroing, dest_predicated, + rdr.reg, READ_REG(rdr)); +#endif // don't check inversion here as dest_pred has already been inverted if (zeroing && (!dest_predicated)) { -- 2.30.2