From 827a0940d2f2b6a16706e4b7b6ef0810761261a5 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Jul 2020 19:31:32 +0100 Subject: [PATCH] missed import of Builder, set cpu_type to "None" temporarily --- src/soc/litex/core.py | 5 +++-- src/soc/litex/sim.py | 16 ++++++++-------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/soc/litex/core.py b/src/soc/litex/core.py index fa73084b..81d01089 100644 --- a/src/soc/litex/core.py +++ b/src/soc/litex/core.py @@ -124,8 +124,9 @@ class LibreSOC(CPU): @staticmethod def elaborate(verilog_filename): cli_params = [] - sdir = get_data_mod("cpu", "libre-soc").data_location - if subprocess.call(["python3", os.path.join(sdir, "cli.py"), + #sdir = get_data_mod("cpu", "libre_soc").data_location + sdir = "./simple" + if subprocess.call(["python3", os.path.join(sdir, "issuer_verilog.py"), *cli_params, verilog_filename], ): raise OSError("Unable to elaborate Libre-SOC CPU, " diff --git a/src/soc/litex/sim.py b/src/soc/litex/sim.py index 24845ec7..cfdc0f8b 100644 --- a/src/soc/litex/sim.py +++ b/src/soc/litex/sim.py @@ -6,8 +6,6 @@ import argparse -from migen import * - from litex.build.generic_platform import Pins, Subsignal from litex.build.sim import SimPlatform from litex.build.sim.config import SimConfig @@ -15,6 +13,7 @@ from litex.build.sim.config import SimConfig from litex.soc.integration.soc import SoCRegion from litex.soc.integration.soc_core import SoCCore from litex.soc.integration.common import get_mem_data +from litex.soc.integration.builder import Builder from litedram.modules import MT41K128M16 from litedram.phy.model import SDRAMPHYModel @@ -64,12 +63,13 @@ class SoCSMP(SoCCore): # SoCCore -------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, - cpu_type = "libre-soc", - cpu_variant=cpu_variant, - cpu_cls=LibreSOC, + cpu_type = "None", # XXX use None for now libre_soc + cpu_variant = cpu_variant, + cpu_cls = LibreSOC, uart_name = "sim", integrated_rom_size = 0x8000, integrated_main_ram_size = 0x00000000) + self.platform.name = "sim" self.add_constant("SIM") @@ -107,7 +107,7 @@ class SoCSMP(SoCCore): if with_sdcard: self.add_sdcard("sdcard", use_emulator=True) -# Build -------------------------------------------------------------------------------------------- +# Build ----------------------------------------------------------------- def main(): parser = argparse.ArgumentParser( @@ -132,14 +132,14 @@ def main(): sim_config.add_module("serial2console", "serial") for i in range(2): - to_run = (i != 0) # first build, then run + to_run = (i != 0) # first build (i=0), then run (i=1) soc = SoCSMP(args.cpu_variant, args.sdram_init and to_run, args.with_sdcard) builder = Builder(soc, compile_gateware = to_run, csr_json = "build/sim/csr.json") builder.build(sim_config=sim_config, - run = i!=0, + run = to_run, opt_level = args.opt_level, trace = args.trace, trace_start = int(args.trace_start), -- 2.30.2