From 82854d7a51e09f8822c924ee5adcf15c4f2142ee Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 10 Dec 2020 17:54:41 +0000
Subject: [PATCH]

---
 openpower/sv/svp_rewrite/svp64/discussion.mdwn | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index b33632921..08a6ab833 100644
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -12,7 +12,7 @@ do not try to jam VL or MAXVL in.  go with the flow of 24 bits spare.
 * 1: select INT or CR predication
 * 3: predicate selection and inversion (QTY 2 for tpred)
 * 4x2 or 3x3: src1/2/3/dest Vector/Scalar reg
-* 3: saturate mode
+* 2: saturate mode
 
 totals: 24 bits (dest elwidth shared)
 
-- 
2.30.2