From 8293c368f8e2ed6aec556c11f0223f4e9ca7b47b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 8 May 2019 02:13:35 +0100 Subject: [PATCH] add names to read/write ports, add priority picker and other pieces --- src/experiment/cscore.py | 65 ++++++++++++++++++++++++++---------- src/regfile/regfile.py | 18 +++++----- src/scoreboard/issue_unit.py | 2 +- 3 files changed, 59 insertions(+), 26 deletions(-) diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py index ecafe5d8..2ba0271d 100644 --- a/src/experiment/cscore.py +++ b/src/experiment/cscore.py @@ -5,24 +5,33 @@ from nmigen import Module, Signal, Array, Elaboratable from regfile.regfile import RegFileArray from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit from scoreboard.fu_fu_matrix import FUFUDepMatrix +from scoreboard.global_pending import GlobalPending +from scoreboard.group_picker import GroupPicker +from scoreboard.issue_unit import IntFPIssueUnit + from alu_hier import Adder, Subtractor class Scoreboard(Elaboratable): - def __init__(self, reg_width, reg_depth): - self.reg_width = reg_width - self.reg_depth = reg_depth + def __init__(self, rwid, n_regs): + """ Inputs: + + * :rwid: bit width of register file(s) - both FP and INT + * :n_regs: depth of register file(s) - number of FP and INT regs + """ + self.rwid = rwid + self.n_regs = n_regs # Register Files - self.intregs = RegFileArray(reg_width, reg_depth) - self.int_dest = self.intregs.write_port() - self.int_src1 = self.intregs.read_port() - self.int_src2 = self.intregs.read_port() + self.intregs = RegFileArray(rwid, n_regs) + self.int_dest = self.intregs.write_port("dest") + self.int_src1 = self.intregs.read_port("src1") + self.int_src2 = self.intregs.read_port("src2") - self.fpregs = RegFileArray(reg_width, reg_depth) - self.fp_dest = self.fpregs.write_port() - self.fp_src1 = self.fpregs.read_port() - self.fp_src2 = self.fpregs.read_port() + self.fpregs = RegFileArray(rwid, n_regs) + self.fp_dest = self.fpregs.write_port("dest") + self.fp_src1 = self.fpregs.read_port("src1") + self.fp_src2 = self.fpregs.read_port("src2") def elaborate(self, platform): m = Module() @@ -30,26 +39,48 @@ class Scoreboard(Elaboratable): m.submodules.fpregs = self.fpregs # Int ALUs - m.submodules.adder = adder = Adder(self.reg_width) - m.submodules.subtractor = subtractor = Subtractor(self.reg_width) + m.submodules.adder = adder = Adder(self.rwid) + m.submodules.subtractor = subtractor = Subtractor(self.rwid) int_alus = [adder, subtractor] # Int FUs il = [] + int_rd_pend_v = [] + int_wr_pend_v = [] for i, a in enumerate(int_alus): - fu = IntFnUnit(self.reg_width, shadow_wid=0) + # set up Integer Function Unit, add to module (and python list) + fu = IntFnUnit(self.rwid, shadow_wid=0) setattr(m.submodules, "intfu%d" % i, fu) il.append(fu) + # collate the read/write pending vectors (to go into global pending) + int_rd_pend_v.append(fu.int_rd_pend_o) + int_wr_pend_v.append(fu.int_wr_pend_o) int_fus = Array(il) - n_fus = len(il) + # Count of number of FUs + n_int_fus = len(il) + n_fp_fus = 0 # for now + + n_fus = n_int_fus + n_fp_fus # plus FP FUs - # FU Dep Matrix - m.submodules.fudeps = fudeps = FUFUDepMatrix(n_fus, n_fus) + # Integer FU Dep Matrix + m.submodules.intfudeps = intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus) + # Integer Priority Picker 1: Adder + Subtractor + m.submodules.intpick1 = GroupPicker(2) # picks between add and sub + # Global Pending Vectors (INT and FP) + # NOTE: number of vectors is NOT same as number of FUs. + m.submodules.g_int_rd_pend_v = GlobalPending(self.rwid, int_rd_pend_v) + m.submodules.g_int_wr_pend_v = GlobalPending(self.rwid, int_wr_pend_v) + + # Issue Unit + m.submodules.issueunit = IntFPIssueUnit(self.rwid, + n_int_fus, + n_fp_fus) return m + def __iter__(self): yield from self.intregs yield from self.fpregs diff --git a/src/regfile/regfile.py b/src/regfile/regfile.py index 1bb5e287..51c920e2 100644 --- a/src/regfile/regfile.py +++ b/src/regfile/regfile.py @@ -13,15 +13,17 @@ class Register(Elaboratable): self._rdports = [] self._wrports = [] - def read_port(self): + def read_port(self, name=None): port = RecordObject([("ren", 1), - ("data_o", self.width)]) + ("data_o", self.width)], + name=name) self._rdports.append(port) return port - def write_port(self): + def write_port(self, name=None): port = RecordObject([("wen", 1), - ("data_i", self.width)]) + ("data_i", self.width)], + name=name) self._wrports.append(port) return port @@ -70,19 +72,19 @@ class RegFileArray(Elaboratable): self._rdports = [] self._wrports = [] - def read_port(self): + def read_port(self, name=None): regs = [] for i in range(self.depth): - port = self.regs[i].read_port() + port = self.regs[i].read_port(name) regs.append(port) regs = Array(regs) self._rdports.append(regs) return regs - def write_port(self): + def write_port(self, name=None): regs = [] for i in range(self.depth): - port = self.regs[i].write_port() + port = self.regs[i].write_port(name) regs.append(port) regs = Array(regs) self._wrports.append(regs) diff --git a/src/scoreboard/issue_unit.py b/src/scoreboard/issue_unit.py index d1f58d11..7b01e8f4 100644 --- a/src/scoreboard/issue_unit.py +++ b/src/scoreboard/issue_unit.py @@ -4,7 +4,7 @@ from nmigen import Module, Signal, Cat, Array, Const, Record, Elaboratable from nmutil.latch import SRLatch from nmigen.lib.coding import Decoder -from shadow_fn import ShadowFn +from .shadow_fn import ShadowFn class IssueUnit(Elaboratable): -- 2.30.2