From 82bff16f120fdce8148c80916ec416d33c8176b0 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 1 Apr 2023 18:57:46 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls010.mdwn | 50 ++++++++++++++++++++----------------- 1 file changed, 27 insertions(+), 23 deletions(-) diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn index 8e32a11fd..9108f243a 100644 --- a/openpower/sv/rfc/ls010.mdwn +++ b/openpower/sv/rfc/ls010.mdwn @@ -161,18 +161,18 @@ Note the deliberate similarity to how VSX register elements are defined: void get_register_element(el_reg_t* el, int gpr, int element, int width) { switch (width) { - case 64: el->dwords = int_regfile[gpr].dwords[element]; - case 32: el->words = int_regfile[gpr].words[element]; - case 16: el->hwords = int_regfile[gpr].hwords[element]; - case 8 : el->bytes = int_regfile[gpr].bytes[element]; + case 64: el->dwords[0] = int_regfile[gpr].dwords[element]; + case 32: el->words[0] = int_regfile[gpr].words[element]; + case 16: el->hwords[0] = int_regfile[gpr].hwords[element]; + case 8 : el->bytes[0] = int_regfile[gpr].bytes[element]; } } void set_register_element(el_reg_t* el, int gpr, int element, int width) { switch (width) { - case 64: int_regfile[gpr].dwords[element] = el->dwords; - case 32: int_regfile[gpr].words[element] = el->words; - case 16: int_regfile[gpr].hwords[element] = el->hwords; - case 8 : int_regfile[gpr].bytes[element] = el->bytes; + case 64: int_regfile[gpr].dwords[element] = el->dwords[0]; + case 32: int_regfile[gpr].words[element] = el->words[0]; + case 16: int_regfile[gpr].hwords[element] = el->hwords[0]; + case 8 : int_regfile[gpr].bytes[element] = el->bytes[0]; } } ``` @@ -207,11 +207,13 @@ write-enable line. It is up to the Hardware Architect to then amortise as simultaneous non-overlapping Register File writes, to achieve High Performance designs. +**Comparative equivalent using VSR registers** + For a comparative data point the VSR Registers may be expressed in the same fashion. The c code below is directly an expression of Figure 97 in Power ISA Public v3.1 Book I Section 6.3 page 258, *after compensating for -MSB0 numbering and adapting in full to LSB0 numbering and obeying LE -ordering*. +MSB0 numbering in both bits abd elements, adapting in full to LSB0 numbering, +and obeying LE ordering*. **Crucial to understanding why the subtraction from 1,3,7,15 is present is because VSX Registers number elements also in MSB0 order**. SVP64 @@ -242,36 +244,38 @@ the numerically-lowest element at the **MSB** end of the register. void get_VSR_element(el_reg_t* el, int gpr, int elt, int width) { check_num_elements(elt, width); switch (width) { - case 64: el->dwords[1-elt] = VSR_regfile[gpr].dwords[1-elt]; - case 32: el->words[3-elt] = VSR_regfile[gpr].words[3-elt]; - case 16: el->hwords[7-elt] = VSR_regfile[gpr].hwords[7-elt]; - case 8 : el->bytes[15-elt] = VSR_regfile[gpr].bytes[15-elt]; + case 64: el->dwords[p] = VSR_regfile[gpr].dwords[1-elt]; + case 32: el->words[0] = VSR_regfile[gpr].words[3-elt]; + case 16: el->hwords[0] = VSR_regfile[gpr].hwords[7-elt]; + case 8 : el->bytes[0] = VSR_regfile[gpr].bytes[15-elt]; } } void set_VSR_element(el_reg_t* el, int gpr, int elt, int width) { check_num_elements(elt, width); switch (width) { - case 64: VSR_regfile[gpr].dwords[elt] = el->dwords[1-elt]; - case 32: VSR_regfile[gpr].words[3-elt] = el->words[3-elt]; - case 16: VSR_regfile[gpr].hwords[7-elt] = el->hwords[7-elt]; - case 8 : VSR_regfile[gpr].bytes[15-elt] = el->bytes[15-elt]; + case 64: VSR_regfile[gpr].dwords[elt] = el->dwords[0]; + case 32: VSR_regfile[gpr].words[3-elt] = el->words[0]; + case 16: VSR_regfile[gpr].hwords[7-elt] = el->hwords[0]; + case 8 : VSR_regfile[gpr].bytes[15-elt] = el->bytes[0]; } } ``` For VSX Registers one key difference is that the overlay of different element -widths is clearly a *bounded quantity*, whereas for Simple-V the elements are -*unrestrained and permitted to flow into successive underlying Scalar registers*. +widths is clearly a *bounded static quantity*, whereas for Simple-V the +elements are +unrestrained and permitted to flow into *successive underlying Scalar registers*. This difference is absolutely critical to a full understanding of the entire Simple-V paradigm and why element-ordering, bit-numbering *and register numbering* are all so strictly defined. -Implementations are not permitted to violate the Canonical definition: software +Implementations are not permitted to violate the Canonical definition. Software will be critically relying on the wrapped (overflow) behaviour inherently -implied from the unbounded c arrays. +implied by the unbounded variable-length c arrays. Illustrating the exact same loop with the exact same effect as achieved by Simple-V -we are first forced to create wrapper functions: +we are first forced to create wrapper functions, to cater for the fact +that VSR register elements are static bounded: ``` int calc_VSR_reg_offs(int elt, int width) { -- 2.30.2