From 82c3bd2e94e7b10d2a1b5b4ed4ee0afc061e2df9 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Sun, 6 Nov 2022 20:06:41 +0300 Subject: [PATCH] power_insn: unify GPR and FPR assembly --- src/openpower/decoder/power_insn.py | 31 +++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 89dbbda8..158c11ab 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1135,15 +1135,31 @@ class ExtendableOperand(DynamicOperand): @_dataclasses.dataclass(eq=True, frozen=True) -class GPROperand(ExtendableOperand): - def assemble(self, value, insn): +class SimpleRegisterOperand(ExtendableOperand): + def assemble(self, value, insn, prefix): + vector = False + if isinstance(value, str): value = value.lower() - if value.startswith("r"): + if value.startswith("%"): + value = value[1:] + if value.startswith("*"): + if not isinstance(insn, SVP64Instruction): + raise ValueError(value) value = value[1:] + vector = True + if value.startswith(prefix): + value = value[len(prefix):] value = int(value, 0) + return super().assemble(value=value, insn=insn) + +@_dataclasses.dataclass(eq=True, frozen=True) +class GPROperand(SimpleRegisterOperand): + def assemble(self, value, insn): + return super().assemble(value=value, insn=insn, prefix="r") + def disassemble(self, insn, verbosity=Verbosity.NORMAL, indent=""): prefix = "" if (verbosity <= Verbosity.SHORT) else "r" @@ -1152,14 +1168,9 @@ class GPROperand(ExtendableOperand): @_dataclasses.dataclass(eq=True, frozen=True) -class FPROperand(ExtendableOperand): +class FPROperand(SimpleRegisterOperand): def assemble(self, value, insn): - if isinstance(value, str): - value = value.lower() - if value.startswith("f"): - value = value[1:] - value = int(value, 0) - return super().assemble(value=value, insn=insn) + return super().assemble(value=value, insn=insn, prefix="f") def disassemble(self, insn, verbosity=Verbosity.NORMAL, indent=""): -- 2.30.2