From 82c3d2b8b9fde3bb01253f8de8b2e6d8d3dad798 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 9 Jun 2021 15:23:34 +0000 Subject: [PATCH] use sys_pllclk_from_pad not sys_clk_from_pad rename module ls180 --- experiments9/build_full_4ksram_recon.sh | 2 +- experiments9/doDesign.py | 2 +- .../non_generated/full_core_4_4ksram_litex_ls180_recon.v | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/experiments9/build_full_4ksram_recon.sh b/experiments9/build_full_4ksram_recon.sh index ba6a0b2..20921bb 100755 --- a/experiments9/build_full_4ksram_recon.sh +++ b/experiments9/build_full_4ksram_recon.sh @@ -21,7 +21,7 @@ make pinmux # clear out make clean -rm *.vst *.ap +rm *.vst *.ap *.blif *.gds # copies over a "full" core #cp non_generated/full_core_4_4ksram_ls180.il ls180.il diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py index 9496838..01866e5 100644 --- a/experiments9/doDesign.py +++ b/experiments9/doDesign.py @@ -61,7 +61,7 @@ def scriptMain (**kw): # ooo, how annoying. nsxlib (only 6 METAL) cannot cope with 3 clocks! #ls180Conf.useHTree('core.por_clk') # output from the PLL, needs to be H-Tree ls180Conf.useHTree('jtag_tck_from_pad') - ls180Conf.useHTree('sys_clk_from_pad') + ls180Conf.useHTree('sys_pllclk_from_pad') ls180ToChip = CoreToChip( ls180Conf ) ls180ToChip.buildChip() diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v index 44a8792..8415590 100644 --- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v @@ -1,7 +1,7 @@ //-------------------------------------------------------------------------------- // Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-06-09 16:10:24 //-------------------------------------------------------------------------------- -module ls180sram4k( +module ls180( input wire uart_tx, input wire uart_rx, output wire i2c_scl, -- 2.30.2