From 82d17615f442555b3577be41e24edd341a11d01d Mon Sep 17 00:00:00 2001 From: =?utf8?q?Samuel=20Iglesias=20Gons=C3=A1lvez?= Date: Wed, 11 Jan 2017 08:17:57 +0100 Subject: [PATCH] i965/fs: clamp exec_size when an instruction has a scalar DF source MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Then the SIMD lowering pass will get rid of any compressed instructions with scalar source (whether force_writemask_all or not) and we avoid hitting the Gen7 region decompression bug. Signed-off-by: Samuel Iglesias Gonsálvez Suggested-by: Francisco Jerez Reviewed-by: Francisco Jerez --- src/intel/compiler/brw_fs.cpp | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 3fc7ae48943..086b1a04855 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -4529,11 +4529,16 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo, */ if (devinfo->gen < 8) { for (unsigned i = 0; i < inst->sources; i++) { + /* IVB implements DF scalars as <0;2,1> regions. */ + const bool is_scalar_exception = is_uniform(inst->src[i]) && + (devinfo->is_haswell || type_sz(inst->src[i].type) != 8); + const bool is_packed_word_exception = + type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 && + type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1; + if (inst->size_written > REG_SIZE && inst->size_read(i) != 0 && inst->size_read(i) <= REG_SIZE && - !is_uniform(inst->src[i]) && - !(type_sz(inst->dst.type) == 4 && inst->dst.stride == 1 && - type_sz(inst->src[i].type) == 2 && inst->src[i].stride == 1)) { + !is_scalar_exception && !is_packed_word_exception) { const unsigned reg_count = DIV_ROUND_UP(inst->size_written, REG_SIZE); max_width = MIN2(max_width, inst->exec_size / reg_count); } -- 2.30.2