From 82ea14fd9d61893514375b6649e0a74a076d4443 Mon Sep 17 00:00:00 2001 From: Andrew Cagney Date: Fri, 27 Mar 1998 04:25:45 +0000 Subject: [PATCH] Define CPU_INDEX. Initialize. For mips_options, iterate over MAX_NR_PROCESSORS when setting options. --- sim/common/ChangeLog | 7 ++++++ sim/common/sim-base.h | 10 +++++++- sim/common/sim-module.c | 7 +++++- sim/mips/ChangeLog | 9 +++++++ sim/mips/interp.c | 54 +++++++++++++++++++++++------------------ 5 files changed, 62 insertions(+), 25 deletions(-) diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index ec3309346b4..b23393bf907 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,10 @@ +Fri Mar 27 14:55:06 1998 Andrew Cagney + + * sim-base.h (CPU_INDEX): Define. + + * sim-utils.c (sim_state_alloc): Initialize. + * sim-module.c (sim_post_argv_init): Ditto. + start-sanitize-am30 Thu Mar 26 10:07:57 1998 Stu Grossman diff --git a/sim/common/sim-base.h b/sim/common/sim-base.h index 654e71e30cd..1c395df2b10 100644 --- a/sim/common/sim-base.h +++ b/sim/common/sim-base.h @@ -1,5 +1,5 @@ /* Simulator pseudo baseclass. - Copyright (C) 1997 Free Software Foundation, Inc. + Copyright (C) 1997-1998 Free Software Foundation, Inc. Contributed by Cygnus Support. This file is part of GDB, the GNU debugger. @@ -174,6 +174,10 @@ typedef struct { struct _bfd *prog_bfd; #define STATE_PROG_BFD(sd) ((sd)->base.prog_bfd) + /* Symbol table for prog_bfd */ + struct symbol_cache_entry **prog_syms; +#define STATE_PROG_SYMS(sd) ((sd)->base.prog_syms) + /* The program's text section. */ struct sec *text_section; /* Starting and ending text section addresses from the bfd. */ @@ -243,6 +247,10 @@ typedef struct { SIM_DESC state; #define CPU_STATE(cpu) ((cpu)->base.state) + /* Processor index within the SD_DESC */ + int index; +#define CPU_INDEX(cpu) ((cpu)->base.index) + /* The name of the cpu. */ const char *name; #define CPU_NAME(cpu) ((cpu)->base.name) diff --git a/sim/common/sim-module.c b/sim/common/sim-module.c index 297b1333508..0fb54717c54 100644 --- a/sim/common/sim-module.c +++ b/sim/common/sim-module.c @@ -87,6 +87,8 @@ sim_pre_argv_init (SIM_DESC sd, const char *myname) } } + sim_config_default (sd); + /* Install all configured in modules. */ if (sim_module_install (sd) != SIM_RC_OK) return SIM_RC_FAIL; @@ -108,7 +110,10 @@ sim_post_argv_init (SIM_DESC sd) /* Set the cpu->state backlinks for each cpu. */ for (i = 0; i < MAX_NR_PROCESSORS; ++i) - CPU_STATE (STATE_CPU (sd, i)) = sd; + { + CPU_STATE (STATE_CPU (sd, i)) = sd; + CPU_INDEX (STATE_CPU (sd, i)) = i; + } return SIM_RC_OK; } diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index d202aa0d598..125e44a4c50 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,12 @@ +Fri Mar 27 15:01:50 1998 Andrew Cagney + + * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS. + +Wed Mar 25 16:44:27 1998 Ian Carmichael + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Regenerated to track ../common/aclocal.m4 changes. + Wed Mar 25 12:35:29 1998 Andrew Cagney * configure: Regenerated to track ../common/aclocal.m4 changes. diff --git a/sim/mips/interp.c b/sim/mips/interp.c index eaf37a2a22a..0dc36e10b2e 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -148,6 +148,12 @@ static void ColdReset PARAMS((SIM_DESC sd)); #define MONITOR_BASE (0xBFC00000) #define MONITOR_SIZE (1 << 11) #define MEM_SIZE (2 << 20) +/* start-sanitize-sky */ +#ifdef TARGET_SKY +#undef MEM_SIZE +#define MEM_SIZE (16 << 20) /* 16 MB */ +#endif +/* end-sanitize-sky */ #if defined(TRACE) static char *tracefile = "trace.din"; /* default filename for trace log */ @@ -177,7 +183,7 @@ mips_option_handler (sd, cpu, opt, arg, is_command) allow external control of the program points being traced (i.e. only from main onwards, excluding the run-time setup, etc.). */ - for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++) + for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++) { sim_cpu *cpu = STATE_CPU (sd, cpu_nr); if (arg == NULL) @@ -571,7 +577,7 @@ sim_write (sd,addr,buffer,size) int cca; if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW)) break; - if (sim_core_write_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1) + if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1) break; } @@ -600,7 +606,7 @@ sim_read (sd,addr,buffer,size) int cca; if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW)) break; - if (sim_core_read_buffer (SD, CPU, sim_core_read_map, buffer + index, paddr, 1) != 1) + if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1) break; } @@ -1539,43 +1545,42 @@ load_memory (SIM_DESC sd, { case AccessLength_QUADWORD : { - unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA, - sim_core_read_map, pAddr); + unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA, read_map, pAddr); value1 = VH8_16 (val); value = VL8_16 (val); break; } case AccessLength_DOUBLEWORD : value = sim_core_read_aligned_8 (cpu, NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); break; case AccessLength_SEPTIBYTE : value = sim_core_read_misaligned_7 (cpu, NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); break; case AccessLength_SEXTIBYTE : value = sim_core_read_misaligned_6 (cpu, NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); break; case AccessLength_QUINTIBYTE : value = sim_core_read_misaligned_5 (cpu, NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); break; case AccessLength_WORD : value = sim_core_read_aligned_4 (cpu, NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); break; case AccessLength_TRIPLEBYTE : value = sim_core_read_misaligned_3 (cpu, NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); break; case AccessLength_HALFWORD : value = sim_core_read_aligned_2 (cpu, NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); break; case AccessLength_BYTE : value = sim_core_read_aligned_1 (cpu, NULL_CIA, - sim_core_read_map, pAddr); + read_map, pAddr); break; default: abort (); @@ -1675,41 +1680,40 @@ store_memory (SIM_DESC sd, case AccessLength_QUADWORD : { unsigned_16 val = U16_8 (MemElem1, MemElem); - sim_core_write_aligned_16 (cpu, NULL_CIA, - sim_core_write_map, pAddr, val); + sim_core_write_aligned_16 (cpu, NULL_CIA, write_map, pAddr, val); break; } case AccessLength_DOUBLEWORD : sim_core_write_aligned_8 (cpu, NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_SEPTIBYTE : sim_core_write_misaligned_7 (cpu, NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_SEXTIBYTE : sim_core_write_misaligned_6 (cpu, NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_QUINTIBYTE : sim_core_write_misaligned_5 (cpu, NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_WORD : sim_core_write_aligned_4 (cpu, NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_TRIPLEBYTE : sim_core_write_misaligned_3 (cpu, NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_HALFWORD : sim_core_write_aligned_2 (cpu, NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; case AccessLength_BYTE : sim_core_write_aligned_1 (cpu, NULL_CIA, - sim_core_write_map, pAddr, MemElem); + write_map, pAddr, MemElem); break; default: abort (); @@ -2928,6 +2932,7 @@ SquareRoot(op,fmt) return(result); } +#if 0 uword64 Max (uword64 op1, uword64 op2, @@ -2995,7 +3000,9 @@ Max (uword64 op1, return(result); } +#endif +#if 0 uword64 Min (uword64 op1, uword64 op2, @@ -3063,6 +3070,7 @@ Min (uword64 op1, return(result); } +#endif uword64 convert (SIM_DESC sd, -- 2.30.2