From 83427c87cd7ba79b978f241f6434e94b9bc41206 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 12 Nov 2015 01:41:23 +0100
Subject: [PATCH] soc/interconnect/stream: add Pipeline

---
 litex/soc/interconnect/stream.py | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index c420f3af..f6b1bb02 100644
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -440,4 +440,23 @@ class Converter(Module):
         else:
             self.comb += Record.connect(self.sink, self.source)
 
+
+class Pipeline(Module):
+    def __init__(self, *modules):
+        n = len(modules)
+        m = modules[0]
+        # expose sink of first module
+        # if available
+        if hasattr(m, "sink"):
+            self.sink = m.sink
+        for i in range(1, n):
+            m_n = modules[i]
+            self.comb += m.source.connect(m_n.sink)
+            m = m_n
+        # expose source of last module
+        # if available
+        if hasattr(m, "source"):
+            self.source = m.source
+
+
 # XXX
-- 
2.30.2