From 834aeb1e52d1af6b0052dcf42e604d2b1852dce8 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Fri, 26 Jul 2019 12:05:23 -0700 Subject: [PATCH] pan/midgard: Extend copy-propagation to swizzles MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit We can compose them when we rewrite, which is.. more code.. but helps. total instructions in shared programs: 3611 -> 3513 (-2.71%) instructions in affected programs: 672 -> 574 (-14.58%) helped: 11 HURT: 2 helped stats (abs) min: 2 max: 14 x̄: 9.09 x̃: 10 helped stats (rel) min: 5.71% max: 24.56% x̄: 17.99% x̃: 18.87% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 1.19% max: 2.08% x̄: 1.64% x̃: 1.64% 95% mean confidence interval for instructions value: -10.45 -4.62 95% mean confidence interval for instructions %-change: -20.07% -9.87% Instructions are helped. total bundles in shared programs: 2117 -> 2067 (-2.36%) bundles in affected programs: 356 -> 306 (-14.04%) helped: 11 HURT: 0 helped stats (abs) min: 1 max: 7 x̄: 4.55 x̃: 5 helped stats (rel) min: 4.55% max: 15.22% x̄: 13.63% x̃: 14.71% 95% mean confidence interval for bundles value: -5.64 -3.45 95% mean confidence interval for bundles %-change: -15.71% -11.55% Bundles are helped. total quadwords in shared programs: 3567 -> 3468 (-2.78%) quadwords in affected programs: 695 -> 596 (-14.24%) helped: 11 HURT: 1 helped stats (abs) min: 2 max: 14 x̄: 9.09 x̃: 10 helped stats (rel) min: 5.56% max: 21.88% x̄: 14.97% x̃: 15.15% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 2.38% max: 2.38% x̄: 2.38% x̃: 2.38% 95% mean confidence interval for quadwords value: -10.96 -5.54 95% mean confidence interval for quadwords %-change: -17.42% -9.63% Quadwords are helped. total registers in shared programs: 391 -> 383 (-2.05%) registers in affected programs: 46 -> 38 (-17.39%) helped: 9 HURT: 1 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 25.00% max: 25.00% x̄: 25.00% x̃: 25.00% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 10.00% max: 10.00% x̄: 10.00% x̃: 10.00% 95% mean confidence interval for registers value: -1.25 -0.35 95% mean confidence interval for registers %-change: -29.42% -13.58% Registers are helped. Signed-off-by: Alyssa Rosenzweig --- src/panfrost/midgard/compiler.h | 1 + src/panfrost/midgard/midgard_opt_copy_prop.c | 21 ++++- src/panfrost/midgard/mir.c | 88 +++++++++++++++++++- 3 files changed, 106 insertions(+), 4 deletions(-) diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h index ba5bc75810b..f428db3123d 100644 --- a/src/panfrost/midgard/compiler.h +++ b/src/panfrost/midgard/compiler.h @@ -431,6 +431,7 @@ void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new); void mir_rewrite_index_dst_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag); void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new); void mir_rewrite_index_src_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag); +void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle); bool mir_single_use(compiler_context *ctx, unsigned value); bool mir_special_index(compiler_context *ctx, unsigned idx); unsigned mir_use_count(compiler_context *ctx, unsigned value); diff --git a/src/panfrost/midgard/midgard_opt_copy_prop.c b/src/panfrost/midgard/midgard_opt_copy_prop.c index c2cf7eb69e3..271c07a1e7a 100644 --- a/src/panfrost/midgard/midgard_opt_copy_prop.c +++ b/src/panfrost/midgard/midgard_opt_copy_prop.c @@ -49,11 +49,26 @@ midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block) if (ins->has_constants) continue; /* Modifier propagation is not handled here */ - if (mir_nontrivial_source2_mod(ins)) continue; + if (mir_nontrivial_source2_mod_simple(ins)) continue; if (mir_nontrivial_outmod(ins)) continue; - /* We're clear -- rewrite */ - mir_rewrite_index_src(ctx, to, from); + /* Texture ops have some weirdness around bias */ + + bool skip = false; + + mir_foreach_instr_global(ctx, q) { + if (q->ssa_args.src1 != to) continue; + if (q->type == TAG_TEXTURE_4) skip = true; + } + + if (skip) + continue; + + /* We're clear -- rewrite, composing the swizzle */ + midgard_vector_alu_src src2 = + vector_alu_from_unsigned(ins->alu.src2); + + mir_rewrite_index_src_swizzle(ctx, to, from, src2.swizzle); mir_remove_instruction(ins); progress |= true; } diff --git a/src/panfrost/midgard/mir.c b/src/panfrost/midgard/mir.c index 225b0680f3f..13dd2d816c9 100644 --- a/src/panfrost/midgard/mir.c +++ b/src/panfrost/midgard/mir.c @@ -34,6 +34,84 @@ void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsign ins->ssa_args.src1 = new; } +static unsigned +mir_get_swizzle(midgard_instruction *ins, unsigned idx) +{ + if (ins->type == TAG_ALU_4) { + unsigned b = (idx == 0) ? ins->alu.src1 : ins->alu.src2; + + midgard_vector_alu_src s = + vector_alu_from_unsigned(b); + + return s.swizzle; + } else if (ins->type == TAG_LOAD_STORE_4) { + assert(idx == 0); + return ins->load_store.swizzle; + } else if (ins->type == TAG_TEXTURE_4) { + switch (idx) { + case 0: + return ins->texture.in_reg_swizzle; + case 1: + /* Swizzle on bias doesn't make sense */ + return 0; + default: + unreachable("Unknown texture source"); + } + } else { + unreachable("Unknown type"); + } +} + +static void +mir_set_swizzle(midgard_instruction *ins, unsigned idx, unsigned new) +{ + if (ins->type == TAG_ALU_4) { + unsigned b = (idx == 0) ? ins->alu.src1 : ins->alu.src2; + + midgard_vector_alu_src s = + vector_alu_from_unsigned(b); + + s.swizzle = new; + unsigned pack = vector_alu_srco_unsigned(s); + + if (idx == 0) + ins->alu.src1 = pack; + else + ins->alu.src2 = pack; + } else if (ins->type == TAG_LOAD_STORE_4) { + ins->load_store.swizzle = new; + } else if (ins->type == TAG_TEXTURE_4) { + switch (idx) { + case 0: + ins->texture.in_reg_swizzle = new; + break; + default: + assert(new == 0); + break; + } + } else { + unreachable("Unknown type"); + } +} + +static void +mir_rewrite_index_src_single_swizzle(midgard_instruction *ins, unsigned old, unsigned new, unsigned swizzle) +{ + if (ins->ssa_args.src0 == old) { + ins->ssa_args.src0 = new; + + mir_set_swizzle(ins, 0, + pan_compose_swizzle(mir_get_swizzle(ins, 0), swizzle)); + } + + if (ins->ssa_args.src1 == old && + !ins->ssa_args.inline_constant) { + ins->ssa_args.src1 = new; + + mir_set_swizzle(ins, 1, + pan_compose_swizzle(mir_get_swizzle(ins, 1), swizzle)); + } +} void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new) @@ -43,6 +121,14 @@ mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new) } } +void +mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle) +{ + mir_foreach_instr_global(ctx, ins) { + mir_rewrite_index_src_single_swizzle(ins, old, new, swizzle); + } +} + void mir_rewrite_index_src_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag) { @@ -153,7 +239,7 @@ mir_nontrivial_source2_mod_simple(midgard_instruction *ins) midgard_vector_alu_src src2 = vector_alu_from_unsigned(ins->alu.src2); - return mir_nontrivial_raw_mod(src2, is_int) && !src2.half; + return mir_nontrivial_raw_mod(src2, is_int) || src2.half; } bool -- 2.30.2