From 83927c63897ec25b2efb5dac58f20a0561d28f26 Mon Sep 17 00:00:00 2001 From: Hongyu Wang Date: Tue, 7 Apr 2020 18:39:53 +0000 Subject: [PATCH] Enable Intel HRESET Instruction gcc/ * common/config/i386/cpuinfo.h (get_available_features): Detect HRESET. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_HRESET_SET, OPTION_MASK_ISA2_HRESET_UNSET): New macros. (ix86_handle_option): Handle -mhreset. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_HRESET. * common/config/i386/i386-isas.h: Add ISA_NAMES_TABLE_ENTRY for hreset. * config.gcc: Add hresetintrin.h * config/i386/hresetintrin.h: New header file. * config/i386/x86gprintrin.h: Include hresetintrin.h. * config/i386/cpuid.h (bit_HRESET): New. * config/i386/i386-builtin.def: Add new builtin. * config/i386/i386-expand.c (ix86_expand_builtin): Handle new builtin. * config/i386/i386-c.c (ix86_target_macros_internal): Define __HRESET__. * config/i386/i386-options.c (isa2_opts): Add -mhreset. (ix86_valid_target_attribute_inner_p): Handle hreset. * config/i386/i386.h (TARGET_HRESET, TARGET_HRESET_P, PTA_HRESET): New. (PTA_ALDERLAKE): Add PTA_HRESET. * config/i386/i386.opt: Add option -mhreset. * config/i386/i386.md (UNSPECV_HRESET): New unspec. (hreset): New define_insn. * doc/invoke.texi: Document -mhreset. * doc/extend.texi: Document hreset. gcc/testsuite/ * gcc.target/i386/hreset-1.c: New test. * gcc.target/i386/funcspec-56.inc: Add new target attribute. * gcc.target/i386/x86gprintrin-1.c: Add -mhreset. * gcc.target/i386/x86gprintrin-2.c: Ditto. * gcc.target/i386/x86gprintrin-3.c: Ditto. * gcc.target/i386/x86gprintrin-4.c: Add mhreset. * gcc.target/i386/x86gprintrin-5.c: Ditto. --- gcc/common/config/i386/cpuinfo.h | 3 ++ gcc/common/config/i386/i386-common.c | 15 ++++++ gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/common/config/i386/i386-isas.h | 1 + gcc/config.gcc | 6 ++- gcc/config/i386/cpuid.h | 1 + gcc/config/i386/hresetintrin.h | 48 +++++++++++++++++++ gcc/config/i386/i386-builtin.def | 3 ++ gcc/config/i386/i386-c.c | 3 +- gcc/config/i386/i386-expand.c | 8 ++++ gcc/config/i386/i386-options.c | 4 +- gcc/config/i386/i386.h | 5 +- gcc/config/i386/i386.md | 11 +++++ gcc/config/i386/i386.opt | 4 ++ gcc/config/i386/x86gprintrin.h | 2 + gcc/doc/extend.texi | 5 ++ gcc/doc/invoke.texi | 7 ++- gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + gcc/testsuite/gcc.target/i386/hreset-1.c | 11 +++++ .../gcc.target/i386/x86gprintrin-1.c | 2 +- .../gcc.target/i386/x86gprintrin-2.c | 2 +- .../gcc.target/i386/x86gprintrin-3.c | 2 +- .../gcc.target/i386/x86gprintrin-4.c | 4 +- .../gcc.target/i386/x86gprintrin-5.c | 4 +- 24 files changed, 140 insertions(+), 14 deletions(-) create mode 100644 gcc/config/i386/hresetintrin.h create mode 100644 gcc/testsuite/gcc.target/i386/hreset-1.c diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 0e63db271f6..1e8324e49b6 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -707,6 +707,9 @@ get_available_features (struct __processor_model *cpu_model, __cpuid_count (7, 1, eax, ebx, ecx, edx); if (eax & bit_AVX512BF16) set_feature (FEATURE_AVX512BF16); + if (eax & bit_HRESET) + set_feature (FEATURE_HRESET); + } } diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c index 6a06383ef0d..bfdca8581c6 100644 --- a/gcc/common/config/i386/i386-common.c +++ b/gcc/common/config/i386/i386-common.c @@ -164,6 +164,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK #define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR +#define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET /* Define a set of ISAs which aren't available when a given ISA is disabled. MMX and SSE ISAs are handled separately. */ @@ -256,6 +257,7 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8 #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16 #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR +#define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -716,6 +718,19 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET; } return true; + + case OPT_mhreset: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET; + } + return true; case OPT_mavx5124fmaps: if (value) diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 3fc2af5c3b1..8c3f7821b9a 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -220,6 +220,7 @@ enum processor_features FEATURE_AMX_INT8, FEATURE_AMX_BF16, FEATURE_UINTR, + FEATURE_HRESET, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index c2dc74171bf..888e325de9e 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -164,4 +164,5 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("amx-int8", FEATURE_AMX_INT8, P_NONE, "-mamx-int8") ISA_NAMES_TABLE_ENTRY("amx-bf16", FEATURE_AMX_BF16, P_NONE, "-mamx-bf16") ISA_NAMES_TABLE_ENTRY("uintr", FEATURE_UINTR, P_NONE, "-muintr") + ISA_NAMES_TABLE_ENTRY("hreset", FEATURE_HRESET, P_NONE, "-mhreset") ISA_NAMES_TABLE_END diff --git a/gcc/config.gcc b/gcc/config.gcc index c02bdddab69..b79c544c9fa 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -413,7 +413,8 @@ i[34567]86-*-*) avx512bf16intrin.h enqcmdintrin.h serializeintrin.h avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h tsxldtrkintrin.h amxtileintrin.h amxint8intrin.h - amxbf16intrin.h x86gprintrin.h uintrintrin.h" + amxbf16intrin.h x86gprintrin.h uintrintrin.h + hresetintrin.h" ;; x86_64-*-*) cpu_type=i386 @@ -449,7 +450,8 @@ x86_64-*-*) avx512bf16intrin.h enqcmdintrin.h serializeintrin.h avx512vp2intersectintrin.h avx512vp2intersectvlintrin.h tsxldtrkintrin.h amxtileintrin.h amxint8intrin.h - amxbf16intrin.h x86gprintrin.h uintrintrin.h" + amxbf16intrin.h x86gprintrin.h uintrintrin.h + hresetintrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index fbc8ca245bd..22d284ea441 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -26,6 +26,7 @@ /* %eax */ #define bit_AVX512BF16 (1 << 5) +#define bit_HRESET (1 << 22) /* %ecx */ #define bit_SSE3 (1 << 0) diff --git a/gcc/config/i386/hresetintrin.h b/gcc/config/i386/hresetintrin.h new file mode 100644 index 00000000000..bdbe253755d --- /dev/null +++ b/gcc/config/i386/hresetintrin.h @@ -0,0 +1,48 @@ +/* Copyright (C) 2020 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#if !defined _X86GPRINTRIN_H_INCLUDED +# error "Never use directly; include instead." +#endif + +#ifndef _HRESETINTRIN_H_INCLUDED +#define _HRESETINTRIN_H_INCLUDED + +#ifndef __HRESET__ +#pragma GCC push_options +#pragma GCC target ("hreset") +#define __DISABLE_HRESET__ +#endif /* __HRESET__ */ + +extern __inline void +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_hreset (unsigned int __EAX) +{ + __builtin_ia32_hreset (__EAX); +} + +#ifdef __DISABLE_HRESET__ +#undef __DISABLE_HRESET__ +#pragma GCC pop_options +#endif /* __DISABLE_HRESET__ */ +#endif /* _HRESETINTRIN_H_INCLUDED. */ diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index bc1b0c7dcec..882cba5dba5 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -457,6 +457,9 @@ BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_UINTR, CODE_FOR_clui, "__builtin_ BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_UINTR, CODE_FOR_stui, "__builtin_ia32_stui", IX86_BUILTIN_STUI, UNKNOWN, (int) VOID_FTYPE_VOID) BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_UINTR, CODE_FOR_senduipi, "__builtin_ia32_senduipi", IX86_BUILTIN_SENDUIPI, UNKNOWN, (int) VOID_FTYPE_UINT64) +/* HRESET */ +BDESC (0, OPTION_MASK_ISA2_HRESET, CODE_FOR_hreset, "__builtin_ia32_hreset", IX86_BUILTIN_HRESET, UNKNOWN, (int) VOID_FTYPE_UNSIGNED) + BDESC_END (SPECIAL_ARGS, ARGS) /* Builtins with variable number of arguments. */ diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 219e1be23e6..bbe9ac5ade1 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -600,7 +600,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__MOVBE__"); if (isa_flag2 & OPTION_MASK_ISA2_UINTR) def_or_undef (parse_in, "__UINTR__"); - + if (isa_flag2 & OPTION_MASK_ISA2_HRESET) + def_or_undef (parse_in, "__HRESET__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index e67c26737b7..02d5ca5783d 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -12825,6 +12825,14 @@ rdseed_step: emit_insn (gen_incssp (mode, op0)); return 0; + case IX86_BUILTIN_HRESET: + icode = CODE_FOR_hreset; + arg0 = CALL_EXPR_ARG (exp, 0); + op0 = expand_normal (arg0); + op0 = force_reg (SImode, op0); + emit_insn (gen_hreset (op0)); + return 0; + case IX86_BUILTIN_RSTORSSP: case IX86_BUILTIN_CLRSSBSY: arg0 = CALL_EXPR_ARG (exp, 0); diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c index 1edc1c8a7b9..82c8091f741 100644 --- a/gcc/config/i386/i386-options.c +++ b/gcc/config/i386/i386-options.c @@ -213,7 +213,8 @@ static struct ix86_target_opts isa2_opts[] = { "-mamx-tile", OPTION_MASK_ISA2_AMX_TILE }, { "-mamx-int8", OPTION_MASK_ISA2_AMX_INT8 }, { "-mamx-bf16", OPTION_MASK_ISA2_AMX_BF16 }, - { "-muintr", OPTION_MASK_ISA2_UINTR } + { "-muintr", OPTION_MASK_ISA2_UINTR }, + { "-mhreset", OPTION_MASK_ISA2_HRESET } }; static struct ix86_target_opts isa_opts[] = { @@ -1041,6 +1042,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("amx-tile", OPT_mamx_tile), IX86_ATTR_ISA ("amx-int8", OPT_mamx_int8), IX86_ATTR_ISA ("amx-bf16", OPT_mamx_bf16), + IX86_ATTR_ISA ("hreset", OPT_mhreset), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index e933b3588c2..e8bde37645a 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -211,6 +211,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_AMX_BF16_P(x) TARGET_ISA2_AMX_BF16(x) #define TARGET_UINTR TARGET_ISA2_UINTR #define TARGET_UINTR_P(x) TARGET_ISA2_UINTR_P(x) +#define TARGET_HRESET TARGET_ISA2_HRESET +#define TARGET_HRESET_P(x) TARGET_ISA2_HRESET_P(x) #define TARGET_LP64 TARGET_ABI_64 #define TARGET_LP64_P(x) TARGET_ABI_64_P(x) @@ -2478,6 +2480,7 @@ const wide_int_bitmask PTA_AMX_TILE(0, HOST_WIDE_INT_1U << 19); const wide_int_bitmask PTA_AMX_INT8(0, HOST_WIDE_INT_1U << 20); const wide_int_bitmask PTA_AMX_BF16(0, HOST_WIDE_INT_1U << 21); const wide_int_bitmask PTA_UINTR (0, HOST_WIDE_INT_1U << 22); +const wide_int_bitmask PTA_HRESET(0, HOST_WIDE_INT_1U << 23); const wide_int_bitmask PTA_X86_64_BASELINE = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR; @@ -2524,7 +2527,7 @@ const wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_COOPERLAKE | PTA_MOVDIRI | PTA_PTWRITE | PTA_WAITPKG | PTA_SERIALIZE | PTA_TSXLDTRK | PTA_AMX_TILE | PTA_AMX_INT8 | PTA_AMX_BF16 | PTA_UINTR; const wide_int_bitmask PTA_ALDERLAKE = PTA_SKYLAKE | PTA_CLDEMOTE | PTA_PTWRITE - | PTA_WAITPKG | PTA_SERIALIZE; + | PTA_WAITPKG | PTA_SERIALIZE | PTA_HRESET; const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD; const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index d712a348ff9..87308165f70 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -316,6 +316,9 @@ ;; For patchable area support UNSPECV_PATCHABLE_AREA + + ;; For HRESET support + UNSPECV_HRESET ]) ;; Constants to represent rounding modes in the ROUND instruction @@ -21703,6 +21706,14 @@ (set_attr "length_immediate" "0") (set_attr "modrm" "0")]) +(define_insn "hreset" + [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")] + UNSPECV_HRESET)] + "TARGET_HRESET" + "hreset\t{$0|0}" + [(set_attr "type" "other") + (set_attr "length" "4")]) + (include "mmx.md") (include "sse.md") (include "sync.md") diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 68f49f53d47..e6b1695febb 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1131,3 +1131,7 @@ Support AMX-INT8 built-in functions and code generation. mamx-bf16 Target Report Mask(ISA2_AMX_BF16) Var(ix86_isa_flags2) Save Support AMX-BF16 built-in functions and code generation. + +mhreset +Target Report Mask(ISA2_HRESET) Var(ix86_isa_flags2) Save +Support HRESET built-in functions and code generation. diff --git a/gcc/config/i386/x86gprintrin.h b/gcc/config/i386/x86gprintrin.h index e35f4b65c9c..ffe07e4519b 100644 --- a/gcc/config/i386/x86gprintrin.h +++ b/gcc/config/i386/x86gprintrin.h @@ -92,6 +92,8 @@ #include +#include + extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _wbinvd (void) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index bd46ebc83cc..62549b02452 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -6643,6 +6643,11 @@ Enable/disable the generation of the AMX-BF16 instructions. @cindex @code{target("uintr")} function attribute, x86 Enable/disable the generation of the UINTR instructions. +@item hreset +@itemx no-hreset +@cindex @code{target("hreset")} function attribute, x86 +Enable/disable the generation of the HRESET instruction. + @item cld @itemx no-cld @cindex @code{target("cld")} function attribute, x86 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 0a5e1e88d21..b997c5123a7 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1364,7 +1364,7 @@ See RS/6000 and PowerPC Options. -mvpclmulqdq -mavx512bitalg -mmovdiri -mmovdir64b -mavx512vpopcntdq @gol -mavx5124fmaps -mavx512vnni -mavx5124vnniw -mprfchw -mrdpid @gol -mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk@gol --mamx-tile -mamx-int8 -mamx-bf16 -muintr@gol +-mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset@gol -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops @gol -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol -mmemcpy-strategy=@var{strategy} -mmemset-strategy=@var{strategy} @gol @@ -30294,6 +30294,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @need 200 @itemx -mamx-bf16 @opindex mamx-bf16 +@need 200 +@itemx -mhreset +@opindex mhreset These switches enable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, @@ -30303,7 +30306,7 @@ WBNOINVD, FMA4, PREFETCHW, RDPID, PREFETCHWT1, RDSEED, SGX, XOP, LWP, XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, PKU, AVX512VBMI2, GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16, ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE, -UINTR or CLDEMOTE extended instruction sets. Each has a corresponding +UINTR, HRESET or CLDEMOTE extended instruction sets. Each has a corresponding @option{-mno-} option to disable use of these instructions. These extensions are also available as built-in functions: see diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc index d6a2e8d2305..02cdc34a385 100644 --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc @@ -75,6 +75,7 @@ extern void test_amx_tile (void) __attribute__((__target__("amx-tile"))); extern void test_amx_int8 (void) __attribute__((__target__("amx-int8"))); extern void test_amx_bf16 (void) __attribute__((__target__("amx-bf16"))); extern void test_uintr (void) __attribute__((__target__("uintr"))); +extern void test_hreset (void) __attribute__((__target__("hreset"))); extern void test_no_sgx (void) __attribute__((__target__("no-sgx"))); extern void test_no_avx5124fmaps(void) __attribute__((__target__("no-avx5124fmaps"))); @@ -151,6 +152,7 @@ extern void test_no_amx_tile (void) __attribute__((__target__("no-amx-tile"))); extern void test_no_amx_int8 (void) __attribute__((__target__("no-amx-int8"))); extern void test_no_amx_bf16 (void) __attribute__((__target__("no-amx-bf16"))); extern void test_no_uintr (void) __attribute__((__target__("no-uintr"))); +extern void test_no_hreset (void) __attribute__((__target__("no-hreset"))); extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona"))); extern void test_arch_core2 (void) __attribute__((__target__("arch=core2"))); diff --git a/gcc/testsuite/gcc.target/i386/hreset-1.c b/gcc/testsuite/gcc.target/i386/hreset-1.c new file mode 100644 index 00000000000..573513f8c58 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/hreset-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mhreset" } */ +/* { dg-final { scan-assembler-times "eax" 1 } } */ +/* { dg-final { scan-assembler-times "hreset\[ \\t\]+\[\$\]\?0" 1 } } */ + +#include + +void foo(unsigned int eax) +{ + _hreset (eax); +} diff --git a/gcc/testsuite/gcc.target/i386/x86gprintrin-1.c b/gcc/testsuite/gcc.target/i386/x86gprintrin-1.c index a65e7d55bbb..293be094b78 100644 --- a/gcc/testsuite/gcc.target/i386/x86gprintrin-1.c +++ b/gcc/testsuite/gcc.target/i386/x86gprintrin-1.c @@ -1,6 +1,6 @@ /* Test that is usable with -O -std=c89 -pedantic-errors. */ /* { dg-do compile } */ -/* { dg-options "-O -std=c89 -pedantic-errors -march=x86-64 -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd -mfsgsbase -mfxsr -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd -mxsave -mxsavec -mxsaveopt -mxsaves -mno-sse -mno-mmx" } */ +/* { dg-options "-O -std=c89 -pedantic-errors -march=x86-64 -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd -mfsgsbase -mfxsr -mhreset -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd -mxsave -mxsavec -mxsaveopt -mxsaves -mno-sse -mno-mmx" } */ /* { dg-additional-options "-muintr" { target { ! ia32 } } } */ #include diff --git a/gcc/testsuite/gcc.target/i386/x86gprintrin-2.c b/gcc/testsuite/gcc.target/i386/x86gprintrin-2.c index ae56e5e9831..c6330275746 100644 --- a/gcc/testsuite/gcc.target/i386/x86gprintrin-2.c +++ b/gcc/testsuite/gcc.target/i386/x86gprintrin-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=x86-64 -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd -mfsgsbase -mfxsr -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd -mxsave -mxsavec -mxsaveopt -mxsaves -mno-sse -mno-mmx" } */ +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=x86-64 -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd -mfsgsbase -mfxsr -mhreset -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd -mxsave -mxsavec -mxsaveopt -mxsaves -mno-sse -mno-mmx" } */ /* { dg-add-options bind_pic_locally } */ /* { dg-additional-options "-muintr" { target { ! ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/x86gprintrin-3.c b/gcc/testsuite/gcc.target/i386/x86gprintrin-3.c index c826acd9f3e..3a7e1f4a10d 100644 --- a/gcc/testsuite/gcc.target/i386/x86gprintrin-3.c +++ b/gcc/testsuite/gcc.target/i386/x86gprintrin-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=x86-64 -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd -mfsgsbase -mfxsr -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd -mxsave -mxsavec -mxsaveopt -mxsaves -mno-sse -mno-mmx" } */ +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=x86-64 -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd -mfsgsbase -mfxsr -mhreset -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd -mxsave -mxsavec -mxsaveopt -mxsaves -mno-sse -mno-mmx" } */ /* { dg-add-options bind_pic_locally } */ /* { dg-additional-options "-muintr" { target { ! ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/x86gprintrin-4.c b/gcc/testsuite/gcc.target/i386/x86gprintrin-4.c index e0aa3a782af..d8a6126e5dc 100644 --- a/gcc/testsuite/gcc.target/i386/x86gprintrin-4.c +++ b/gcc/testsuite/gcc.target/i386/x86gprintrin-4.c @@ -15,9 +15,9 @@ #ifndef DIFFERENT_PRAGMAS #ifdef __x86_64__ -#pragma GCC target ("adx,bmi,bmi2,fsgsbase,fxsr,lwp,lzcnt,popcnt,rdrnd,rdseed,tbm,rtm,serialize,tsxldtrk,uintr,xsaveopt") +#pragma GCC target ("adx,bmi,bmi2,fsgsbase,fxsr,hreset,lwp,lzcnt,popcnt,rdrnd,rdseed,tbm,rtm,serialize,tsxldtrk,uintr,xsaveopt") #else -#pragma GCC target ("adx,bmi,bmi2,fsgsbase,fxsr,lwp,lzcnt,popcnt,rdrnd,rdseed,tbm,rtm,serialize,tsxldtrk,xsaveopt") +#pragma GCC target ("adx,bmi,bmi2,fsgsbase,fxsr,hreset,lwp,lzcnt,popcnt,rdrnd,rdseed,tbm,rtm,serialize,tsxldtrk,xsaveopt") #endif #endif diff --git a/gcc/testsuite/gcc.target/i386/x86gprintrin-5.c b/gcc/testsuite/gcc.target/i386/x86gprintrin-5.c index a28c16a90e3..9ef66fdad54 100644 --- a/gcc/testsuite/gcc.target/i386/x86gprintrin-5.c +++ b/gcc/testsuite/gcc.target/i386/x86gprintrin-5.c @@ -28,9 +28,9 @@ #define __builtin_ia32_xabort(M) __builtin_ia32_xabort(1) #ifdef __x86_64__ -#pragma GCC target ("adx,bmi,bmi2,clflushopt,clwb,clzero,enqcmd,fsgsbase,fxsr,lwp,lzcnt,mwaitx,pconfig,pku,popcnt,rdpid,rdrnd,rdseed,tbm,rtm,serialize,sgx,tsxldtrk,uintr,xsavec,xsaveopt,xsaves,wbnoinvd") +#pragma GCC target ("adx,bmi,bmi2,clflushopt,clwb,clzero,enqcmd,fsgsbase,fxsr,hreset,lwp,lzcnt,mwaitx,pconfig,pku,popcnt,rdpid,rdrnd,rdseed,tbm,rtm,serialize,sgx,tsxldtrk,uintr,xsavec,xsaveopt,xsaves,wbnoinvd") #else -#pragma GCC target ("adx,bmi,bmi2,clflushopt,clwb,clzero,enqcmd,fsgsbase,fxsr,lwp,lzcnt,mwaitx,pconfig,pku,popcnt,rdpid,rdrnd,rdseed,tbm,rtm,serialize,sgx,tsxldtrk,xsavec,xsaveopt,xsaves,wbnoinvd") +#pragma GCC target ("adx,bmi,bmi2,clflushopt,clwb,clzero,enqcmd,fsgsbase,fxsr,hreset,lwp,lzcnt,mwaitx,pconfig,pku,popcnt,rdpid,rdrnd,rdseed,tbm,rtm,serialize,sgx,tsxldtrk,xsavec,xsaveopt,xsaves,wbnoinvd") #endif #include -- 2.30.2