From 83c441f2f43140c93a8248a235c4bf1962b4666c Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Mon, 11 May 2020 11:15:37 -0400 Subject: [PATCH] Add ability to specify initial state for SPRs --- src/soc/alu/test/test_pipe_caller.py | 8 ++++---- src/soc/decoder/isa/caller.py | 10 ++++++---- src/soc/decoder/isa/test_caller.py | 4 ++-- src/soc/decoder/pseudo/pywriter.py | 4 ++-- 4 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py index faad0eb5..4f58f9b9 100644 --- a/src/soc/alu/test/test_pipe_caller.py +++ b/src/soc/alu/test/test_pipe_caller.py @@ -54,7 +54,7 @@ def set_alu_inputs(alu, dec2, sim): class ALUTestCase(FHDLTestCase): - def run_tst(self, program, initial_regs): + def run_tst(self, program, initial_regs, initial_sprs): m = Module() comb = m.d.comb instruction = Signal(32) @@ -71,7 +71,7 @@ class ALUTestCase(FHDLTestCase): comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e) comb += alu.p.valid_i.eq(1) comb += alu.n.ready_i.eq(1) - simulator = ISA(pdecode2, initial_regs) + simulator = ISA(pdecode2, initial_regs, initial_sprs) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) gen = program.generate_instructions() @@ -116,8 +116,8 @@ class ALUTestCase(FHDLTestCase): sim.run() return simulator - def run_tst_program(self, prog, initial_regs=[0] * 32): - simulator = self.run_tst(prog, initial_regs) + def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}): + simulator = self.run_tst(prog, initial_regs, initial_sprs) simulator.gpr.dump() return simulator diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 8a244a3e..e2a4f89d 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -137,9 +137,10 @@ class PC: class SPR(dict): - def __init__(self, dec2): + def __init__(self, dec2, initial_sprs={}): self.sd = dec2 dict.__init__(self) + self.update(initial_sprs) def __getitem__(self, key): # if key in special_sprs get the special spr, otherwise return key @@ -166,11 +167,11 @@ class SPR(dict): class ISACaller: # decoder2 - an instance of power_decoder2 # regfile - a list of initial values for the registers - def __init__(self, decoder2, regfile): + def __init__(self, decoder2, regfile, initial_sprs={}): self.gpr = GPR(decoder2, regfile) self.mem = Mem() self.pc = PC() - self.spr = SPR(decoder2) + self.spr = SPR(decoder2, initial_sprs) # TODO, needed here: # FPR (same as GPR except for FP nums) # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR) @@ -199,8 +200,8 @@ class ISACaller: 'CR': self.cr, 'undefined': self.undefined, 'mode_is_64bit': True, + 'SO': XER_bits['SO'] } - self.namespace.update(XER_bits) # field-selectable versions of Condition Register TODO check bitranges? self.crl = [] @@ -235,6 +236,7 @@ class ISACaller: self.namespace[name] = SelectableInt(val, sig.width) self.namespace['XER'] = self.spr['XER'] + self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value def handle_carry(self, inputs, outputs): inv_a = yield self.dec2.invert_a diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 29ebb5d6..f1224f48 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -19,7 +19,7 @@ class Register: class DecoderTestCase(FHDLTestCase): - def run_tst(self, generator, initial_regs): + def run_tst(self, generator, initial_regs, initial_sprs={}): m = Module() comb = m.d.comb instruction = Signal(32) @@ -27,7 +27,7 @@ class DecoderTestCase(FHDLTestCase): pdecode = create_pdecode() m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - simulator = ISA(pdecode2, initial_regs) + simulator = ISA(pdecode2, initial_regs, initial_sprs) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) gen = generator.generate_instructions() diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py index a55b3ffc..95eb13c7 100644 --- a/src/soc/decoder/pseudo/pywriter.py +++ b/src/soc/decoder/pseudo/pywriter.py @@ -116,8 +116,8 @@ class PyISAWriter(ISA): classes = ', '.join(['ISACaller'] + self.pages_written) f.write('class ISA(%s):\n' % classes) - f.write(' def __init__(self, dec, regs):\n') - f.write(' super().__init__(dec, regs)\n') + f.write(' def __init__(self, dec, regs, sprs):\n') + f.write(' super().__init__(dec, regs, sprs)\n') f.write(' self.instrs = {\n') for page in self.pages_written: f.write(' **self.%s_instrs,\n' % page) -- 2.30.2