From 83d3ca284984623383cb03d7d0b05d0865b3442c Mon Sep 17 00:00:00 2001 From: Aaron Sawdey Date: Wed, 12 Oct 2016 02:12:06 +0000 Subject: [PATCH] re PR target/77934 (pattern for mtvsrdd needs to use b constraint not r) 2016-10-12 Aaron Sawdey PR target/77934 * config/rs6000/vmx.md (vsx_concat_): The mtvsrdd instruction needs a base register for arg 1. From-SVN: r241017 --- gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/vsx.md | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6facb484ff8..a3e77945859 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-10-12 Aaron Sawdey + + PR target/77934 + * config/rs6000/vmx.md (vsx_concat_): The mtvsrdd instruction + needs a base register for arg 1. + 2016-10-12 Jakub Jelinek * common.opt (Wimplicit-fallthrough) Turn into alias to diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 359e424d6b4..0f650242da4 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1938,8 +1938,8 @@ (define_insn "vsx_concat_" [(set (match_operand:VSX_D 0 "gpc_reg_operand" "=,we") (vec_concat:VSX_D - (match_operand: 1 "gpc_reg_operand" ",r") - (match_operand: 2 "gpc_reg_operand" ",r")))] + (match_operand: 1 "gpc_reg_operand" ",b") + (match_operand: 2 "gpc_reg_operand" ",b")))] "VECTOR_MEM_VSX_P (mode)" { if (which_alternative == 0) -- 2.30.2