From 83edefe97d77ec6faeb2331337baecfe842f34c9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 24 Jun 2018 14:24:11 +0100 Subject: [PATCH] add cell outen wires --- src/test_bsv/pinmux.bsv | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/src/test_bsv/pinmux.bsv b/src/test_bsv/pinmux.bsv index 7962109..2fea0b5 100644 --- a/src/test_bsv/pinmux.bsv +++ b/src/test_bsv/pinmux.bsv @@ -88,17 +88,20 @@ package pinmux; Wire#(Bit#(1)) wrcell2_mux<-mkDWire(0); // following wires capture signals to IO CELL if io-0 is // allotted to it - GenericIOType cell0_mux_out=unpack(0); + Wire#(Bit#(1)) cell0_mux_out<-mkDWire(0); + Wire#(Bit#(1)) cell0_mux_outen<-mkDWire(0); Wire#(Bit#(1)) cell0_mux_in<-mkDWire(0); // following wires capture signals to IO CELL if io-1 is // allotted to it - GenericIOType cell1_mux_out=unpack(0); + Wire#(Bit#(1)) cell1_mux_out<-mkDWire(0); + Wire#(Bit#(1)) cell1_mux_outen<-mkDWire(0); Wire#(Bit#(1)) cell1_mux_in<-mkDWire(0); // following wires capture signals to IO CELL if io-2 is // allotted to it - GenericIOType cell2_mux_out=unpack(0); + Wire#(Bit#(1)) cell2_mux_out<-mkDWire(0); + Wire#(Bit#(1)) cell2_mux_outen<-mkDWire(0); Wire#(Bit#(1)) cell2_mux_in<-mkDWire(0); // following wires capture signals to IO CELL if uart-0 is @@ -225,6 +228,14 @@ package pinmux; wrcell2_mux==1?0: twi0_scl_io; + // TODO: here is needed something which sets a new + // wire, cell2_mux_outen + cell2_mux_outen= + wrcell2_mux==0?gpioa_a2_io.output_en: + wrcell2_mux==1?0: + twi0_scl_io.output_en; + + rule assign_wrgpioa_a2_in_on_cell2(wrcell2_mux==0); wrgpioa_a2_in<=cell2_mux_in; endrule -- 2.30.2