From 8401717964abe249b3b7b0b5e432f778c6f45b6f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 16 Feb 2022 12:33:11 +0000 Subject: [PATCH] fix ECP5DDRPHY cs declaration --- gram/phy/ecp5ddrphy.py | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index 752d021..17098b1 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -139,7 +139,9 @@ class ECP5DDRPHY(Peripheral, Elaboratable): addressbits = len(self.pads.a.o0) bankbits = len(self.pads.ba.o0) - nranks = 1 if not hasattr(self.pads, "cs") else len(self.pads.cs.o0) + nranks = 1 + if hasattr(self.pads, "cs") and hasattr(self.pads.cs, "o0"): + nranks = len(self.pads.cs.o0) databits = len(self.pads.dq.io) self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4) @@ -147,7 +149,6 @@ class ECP5DDRPHY(Peripheral, Elaboratable): tck = 1/(2*self._sys_clk_freq) nphases = 2 databits = len(self.pads.dq.io) - nranks = 1 if not hasattr(self.pads, "cs") else len(self.pads.cs.o0) cl, cwl = get_cl_cw("DDR3", tck) cl_sys_latency = get_sys_latency(nphases, cl) cwl_sys_latency = get_sys_latency(nphases, cwl) @@ -241,16 +242,20 @@ class ECP5DDRPHY(Peripheral, Elaboratable): if hasattr(self.pads, "cs"): controls.append("cs") for name in controls: + print ("clock", name, getattr(self.pads, name)) + pad = getattr(self.pads, name) + if not hasattr(pad, "o_clk"): + continue m.d.comb += [ - getattr(self.pads, name).o_clk.eq(ClockSignal("dramsync")), - getattr(self.pads, name).o_fclk.eq(ClockSignal("sync2x")), + pad.o_clk.eq(ClockSignal("dramsync")), + pad.o_fclk.eq(ClockSignal("sync2x")), ] - for i in range(len(getattr(self.pads, name).o0)): + for i in range(len(pad.o0)): m.d.comb += [ - getattr(self.pads, name).o0[i].eq(getattr(dfi.phases[0], name)[i]), - getattr(self.pads, name).o1[i].eq(getattr(dfi.phases[0], name)[i]), - getattr(self.pads, name).o2[i].eq(getattr(dfi.phases[1], name)[i]), - getattr(self.pads, name).o3[i].eq(getattr(dfi.phases[1], name)[i]), + pad.o0[i].eq(getattr(dfi.phases[0], name)[i]), + pad.o1[i].eq(getattr(dfi.phases[0], name)[i]), + pad.o2[i].eq(getattr(dfi.phases[1], name)[i]), + pad.o3[i].eq(getattr(dfi.phases[1], name)[i]), ] # DQ --------------------------------------------------------------------------------------- -- 2.30.2