From 8446f87e840357d33af9966a2d881ba12a19f5e3 Mon Sep 17 00:00:00 2001
From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Tue, 26 May 2020 17:22:35 +0000
Subject: [PATCH] [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise
 that RA (src1) can be zero

---
 26/5e84245a013ccca391b835386171fe8724938b | 89 +++++++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 26/5e84245a013ccca391b835386171fe8724938b

diff --git a/26/5e84245a013ccca391b835386171fe8724938b b/26/5e84245a013ccca391b835386171fe8724938b
new file mode 100644
index 0000000..b905dc2
--- /dev/null
+++ b/26/5e84245a013ccca391b835386171fe8724938b
@@ -0,0 +1,89 @@
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+From: bugzilla-daemon@libre-soc.org
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Tue, 26 May 2020 17:22:35 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
+X-Bugzilla-Resolution: 
+X-Bugzilla-Priority: ---
+X-Bugzilla-Assigned-To: cestrauss@gmail.com
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+Message-ID: <bug-336-13-mCDxTGLlgX@https.bugs.libre-soc.org/>
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+References: <bug-336-13@https.bugs.libre-soc.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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-- 
2.30.2