From 844cf810b53ed39884aabcbbfeb418fc1750e03f Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Fri, 15 May 2020 15:36:35 -0400 Subject: [PATCH] Implement ctr decrementing --- src/soc/branch/main_stage.py | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py index f2a9370c..341d141b 100644 --- a/src/soc/branch/main_stage.py +++ b/src/soc/branch/main_stage.py @@ -70,9 +70,21 @@ class BranchMainStage(PipeModBase): bc_taken = Signal(reset_less=True) with m.If(bo[2]): comb += bc_taken.eq((cr_bit == bo[3]) | bo[4]) - - ######## main switch statement ######## - + with m.Else(): + # Yes, the CTR only counts 32 bits + ctr = Signal(64, reset_less=True) + comb += ctr.eq(self.i.spr - 1) + comb += self.o.spr.data.eq(ctr) + comb += self.o.spr.ok.eq(1) + ctr_eq_zero = Signal(reset_less=True) + with m.If(bo[3:4] == 0b00): + comb += bc_taken.eq(~cr_bit & (ctr_eq_zero == bo[1])) + with m.Elif(bo[3:4] == 0b01): + comb += bc_taken.eq(cr_bit & (ctr_eq_zero == bo[1])) + with m.Elif(bo[4] == 1): + comb += bc_taken.eq(ctr_eq_zero == bo[1]) + + ### Main Switch Statement ### with m.Switch(op.insn_type): #### branch #### with m.Case(InternalOp.OP_B): -- 2.30.2