From 846a1d66bec5d62913acb5903fcbb026f7708d67 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 29 Aug 2020 16:27:23 +0100 Subject: [PATCH] investigating CR mtocrf / mfocrf --- src/soc/decoder/power_decoder2.py | 3 ++- src/soc/decoder/selectable_int.py | 2 +- src/soc/litex/florent/sim.py | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 0f2a4860..b16a30d0 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -489,7 +489,8 @@ class DecodeCRIn(Elaboratable): def elaborate(self, platform): m = Module() - m.submodules.ppick = ppick = PriorityPicker(8)#reverse_i=True) + m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True, + reverse_o=True) comb = m.d.comb op = self.dec.op diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py index 2811a959..575d1d87 100644 --- a/src/soc/decoder/selectable_int.py +++ b/src/soc/decoder/selectable_int.py @@ -298,7 +298,7 @@ class SelectableInt: def __setitem__(self, key, value): if isinstance(key, SelectableInt): key = key.value - print("setitem", key, self.bits, hex(self.value), hex(value.value)) + print("setitem", key, self.bits, hex(self.value)) if isinstance(key, int): assert key < self.bits assert key >= 0 diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index 3b693fda..b0fd474e 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -50,6 +50,7 @@ class LibreSoCSim(SoCSDRAM): # "hello_world/hello_world.bin" ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ "tests/1.bin" + #ram_fname = "/tmp/test.bin" #ram_fname = None ram_init = [] @@ -289,7 +290,7 @@ class LibreSoCSim(SoCSDRAM): ) if cpu == "libresoc": - self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x105ec)) + self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x1094c)) #self.comb += active_dbg_cr.eq(1) # get the CR -- 2.30.2